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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from IA0PR11MB7307.namprd11.prod.outlook.com (2603:10b6:208:437::10) by MN6PR11MB8147.namprd11.prod.outlook.com (2603:10b6:208:46f::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.19; Tue, 28 Oct 2025 07:51:29 +0000 Received: from IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843]) by IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843%6]) with mapi id 15.20.9253.017; Tue, 28 Oct 2025 07:51:29 +0000 Message-ID: <3f7e975f-76b0-4ba8-980c-e9e9df7e6e37@intel.com> Date: Tue, 28 Oct 2025 13:21:22 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/26] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy To: Suraj Kandpal , , CC: , , , References: <20251024100712.3776261-1-suraj.kandpal@intel.com> <20251024100712.3776261-6-suraj.kandpal@intel.com> Content-Language: en-US From: "Murthy, Arun R" In-Reply-To: <20251024100712.3776261-6-suraj.kandpal@intel.com> Content-Type: text/plain; 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> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); > void intel_cx0_setup_powerdown(struct intel_encoder *encoder); > +bool intel_cx0_is_hdmi_frl(u32 clock); > int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); > void intel_cx0_pll_power_save_wa(struct intel_display *display); > void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index c65333cc9494..b6f71425cd19 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -11,6 +11,7 @@ > #include "intel_de.h" > #include "intel_display.h" > #include "intel_display_types.h" > +#include "intel_hdmi.h" > #include "intel_lt_phy.h" > #include "intel_lt_phy_regs.h" > #include "intel_tc.h" > @@ -108,13 +109,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, > intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0); > } > > +static void > +intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + bool lane_reversal) > +{ > + struct intel_display *display = to_intel_display(encoder); > + u32 val = 0; > + > + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), > + XELPDP_PORT_REVERSAL, > + lane_reversal ? XELPDP_PORT_REVERSAL : 0); > + > + val |= XELPDP_FORWARD_CLOCK_UNGATE; > + > + /* > + * We actually mean MACCLK here and not MAXPCLK when using LT Phy > + * but since the register bits still remain the same we use > + * the same definition > + */ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && > + intel_hdmi_is_frl(crtc_state->port_clock)) > + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); > + else > + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > + > + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), > + XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | > + XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | > + XELPDP_SSC_ENABLE_PLLB, val); > +} > + > void intel_lt_phy_pll_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > + bool lane_reversal = dig_port->lane_reversal; > + > /* 1. Enable MacCLK at default 162 MHz frequency. */ > intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); > > /* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */ > + intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal); > + > /* 3. Change owned PHY lanes power to Ready state. */ > /* > * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,