From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug Date: Fri, 1 Feb 2019 02:03:17 +0000 Message-ID: <42d583cbe0abe4aab8136a289d7e9a41b706510d.camel@intel.com> References: <20190131005821.24662-1-jose.souza@intel.com> <992008a3-0cc1-9755-ebb2-dded629c28de@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2014536580==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D16436E23D for ; Fri, 1 Feb 2019 02:03:18 +0000 (UTC) In-Reply-To: <992008a3-0cc1-9755-ebb2-dded629c28de@linux.intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "maarten.lankhorst@linux.intel.com" Cc: "Pandiyan, Dhinakaran" List-Id: intel-gfx@lists.freedesktop.org --===============2014536580== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-V+8zY5/6QVNhfkk0B+Gl" --=-V+8zY5/6QVNhfkk0B+Gl Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2019-01-31 at 10:34 +0100, Maarten Lankhorst wrote: > Op 31-01-2019 om 01:58 schreef Jos=C3=A9 Roberto de Souza: > > Changing the i915_edp_psr_debug was enabling, disabling or > > switching > > PSR version by directly calling intel_psr_disable_locked() and > > intel_psr_enable_locked(), what is not the default PSR path that > > will > > be executed by real users. > >=20 > > So lets force a fastset in the PSR CRTC to trigger a pipe update > > and > > stress the default code path. > >=20 > > Recently a bug was found when switching from PSR2 to PSR1 while > > enable_psr kernel parameter was set to the default parameter, this > > changes fix it and also fixes the bug linked bellow were DRRS was > > left enabled together with PSR when enabling PSR from debugfs. > >=20 > > v2: Handling missing case: disabled to PSR1 > >=20 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D108341 > > Cc: Maarten Lankhorst > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > >=20 > > Should I add IGT tests to test every state switch combination? >=20 > Should probably be done for DRRS as well. We should be able to stop > having to set has_drrs and has_psr unconditionally then. :) > Could be a separate followup patch. I have DRRS/PSR bugs assigned to me, I will definitely fix that in the future. >=20 > The complete duplication of the whole atomic state is overkill and > should be avoided, just use=20 > if (!intel_crtc_has_type(to_intel_crtc_state(crtc->state), > INTEL_OUTPUT_EDP) > continue; >=20 > crtc_state =3D drm_atomic_get_old_crtc_state(...) > .... >=20 > And then do a normal commit. We will add all planes and connectors as > needed. Thanks for the suggestion, just sent the new version with this. >=20 > With that fixed: > Reviewed-by: Maarten Lankhorst >=20 --=-V+8zY5/6QVNhfkk0B+Gl Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlxTqOMACgkQVenbO/mO WkmLEggAqSR3qGCE/n57cHIn2OV05Nmbpmw6OrHiPpjgdHAUUYZXjf5HtQPTfjdC z+xmhjtcscAPsKy3vZrnBcJGPQD13gcXxlznkXtXxcbV4kCAwM/v+1+po3A+qjCb kPzasnJGhYHZRMswQDElZdRsSsbj35wKHHE7twaIt7iKLqMHkHzqDoixC3+mzF/T tSODC/6irmmhi6jGvZ3tZyRSK/sBz+qx4JqmIPKSyBTsw07oUzIvPbo9nwlwFD47 T7A2KnpqbuqU0cqExiWaJdasrqkfujHo5ZcMR0HLP+Sexvn6EYZOZW6WCIIqnigW sv1cvN9w4AHIE0bWVScNdHURPvsnYQ== =8Cj+ -----END PGP SIGNATURE----- --=-V+8zY5/6QVNhfkk0B+Gl-- --===============2014536580== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============2014536580==--