From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kenneth Graunke Subject: Re: [PATCH] drm/i915: Make sample_c messages go faster on Haswell. Date: Thu, 30 Oct 2014 02:32:40 -0700 Message-ID: <4380504.nITrtgCgRI@vakarian> References: <1414620763-2841-1-git-send-email-kenneth@whitecape.org> <20141030085003.GQ10649@intel.com> <20141030090051.GR10649@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0256495996==" Return-path: Received: from smtp129.dfw.emailsrvr.com (smtp129.dfw.emailsrvr.com [67.192.241.129]) by gabe.freedesktop.org (Postfix) with ESMTP id 65C056E6F4 for ; Thu, 30 Oct 2014 02:29:40 -0700 (PDT) In-Reply-To: <20141030090051.GR10649@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0256495996== Content-Type: multipart/signed; boundary="nextPart1459160.80dNgsq1GU"; micalg="pgp-sha1"; protocol="application/pgp-signature" --nextPart1459160.80dNgsq1GU Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" On Thursday, October 30, 2014 11:00:51 AM Ville Syrj=E4l=E4 wrote: > On Thu, Oct 30, 2014 at 10:50:03AM +0200, Ville Syrj=E4l=E4 wrote: > > On Wed, Oct 29, 2014 at 03:12:43PM -0700, Kenneth Graunke wrote: > > > Haswell significantly improved the performance of sampler_c messa= ges, > > > but the optimization appears to be off by default. Later platfor= ms > > > remove this bit, and apparently always enable the optimization. > > >=20 > > > Improves performance in "Counter Strike: Global Offensive" by 18%= > > > at default settings on Iris Pro. No Piglit regressions. > >=20 > > Nice. We need more bits like this ;) > >=20 > > >=20 > > > Signed-off-by: Kenneth Graunke > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > > > 2 files changed, 5 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h=20 b/drivers/gpu/drm/i915/i915_reg.h > > > index 77fce96..340821a 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -5952,6 +5952,7 @@ enum punit_power_well { > > > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > > =20 > > > #define HALF_SLICE_CHICKEN3=09=090xe184 > > > +#define HSW_SAMPLE_C_PERFORMANCE=09(1<<9) > > > #define GEN8_CENTROID_PIXEL_OPT_DIS=09(1<<8) > > > #define GEN8_SAMPLER_POWER_BYPASS_DIS=09(1<<1) > > > =20 > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c=20 b/drivers/gpu/drm/i915/intel_pm.c > > > index 7a69eba..50c72a7 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -5736,6 +5736,10 @@ static void haswell_init_clock_gating(stru= ct=20 drm_device *dev) > > > =09I915_WRITE(GEN7_GT_MODE, > > > =09=09 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); > > > =20 > > > +=09/* Make sample_c messages faster. */ > >=20 > > I found a name for it in the w/a database. > >=20 > > WaSampleCChickenBitEnable:hsw > >=20 > > Reviewed-by: Ville Syrj=E4l=E4 >=20 > Oh actually it says palette won't work when this bit is on. I'm assum= ing > that's the texture palette. Do we have any use of that anywhere? That's a good point. 3DSTATE_SAMPLER_PALETTE_LOAD and the A8P8/indexed= =20 formats aren't used by Mesa or xf86-video-intel, but it looks like they= might=20 be used by libva. Can someone confirm that libva does use the sampler palette? If they do, what do we do about it? =2D-Ken --nextPart1459160.80dNgsq1GU Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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