From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/3] drm/i915: disable wc gtt pte mappings on gen2 Date: Wed, 10 Oct 2012 23:37:36 +0100 Message-ID: <453bf0$61is0t@azsmga001.ch.intel.com> References: <1349903641-18378-1-git-send-email-daniel.vetter@ffwll.ch> <1349903641-18378-3-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F8549E8BC for ; Wed, 10 Oct 2012 15:38:00 -0700 (PDT) In-Reply-To: <1349903641-18378-3-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 10 Oct 2012 23:14:01 +0200, Daniel Vetter wrote: > It doesn't work since the gtt pte range sits in the middle of the mmio > bar. We didn't notice that since both my and Chris' gen2 machines > don't support PAT and hence all wc io mapping request will > automatically be demoted to uc. > > This regression has been introduce in > > commit edef7e685da05c13cce50c0126189c80fe2c8f71 > Author: Chris Wilson > Date: Fri Sep 14 11:57:47 2012 +0100 > > agp/intel: Use a write-combining map for updating PTEs > > Reported-by: Egbert Eich > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834 > Signed-off-by: Daniel Vetter Thanks for the explanation, Acked-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre