From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2 2/5] drm/i915/cnl+: Move the combo PHY init/uninit code to a new file Date: Wed, 7 Nov 2018 20:41:08 +0000 Message-ID: <46454e4c7e628515c7560ecbbb7bc1790b9d240d.camel@intel.com> References: <20181106160621.23057-1-imre.deak@intel.com> <20181106160621.23057-3-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2091536211==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6536A6E4A6 for ; Wed, 7 Nov 2018 20:41:11 +0000 (UTC) In-Reply-To: <20181106160621.23057-3-imre.deak@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Deak, Imre" Cc: "Zanoni, Paulo R" , "Vivi, Rodrigo" List-Id: intel-gfx@lists.freedesktop.org --===============2091536211== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-6KW09arE5kxOLZucBoUp" --=-6KW09arE5kxOLZucBoUp Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2018-11-06 at 18:06 +0200, Imre Deak wrote: > Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code > in a > separate file. >=20 > No functional change. >=20 > v2: > - Use SPDX license tag instead of boilerplate. (Rodrigo) >=20 > Suggested-by: Ville Syrj=C3=A4l=C3=A4 > Cc: Paulo Zanoni > Cc: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jos=C3=A9 Roberto de Souza > Cc: Jos=C3=A9 Roberto de Souza > Cc: Rodrigo Vivi > Signed-off-by: Imre Deak > Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/i915_drv.h | 6 ++ > drivers/gpu/drm/i915/intel_combo_phy.c | 141 > ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 127 ++------------------ > -------- > 4 files changed, 156 insertions(+), 119 deletions(-) > create mode 100644 drivers/gpu/drm/i915/intel_combo_phy.c >=20 > diff --git a/drivers/gpu/drm/i915/Makefile > b/drivers/gpu/drm/i915/Makefile > index 6fbda5977658..0ff878c994e2 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -113,6 +113,7 @@ i915-y +=3D intel_audio.o \ > intel_bios.o \ > intel_cdclk.o \ > intel_color.o \ > + intel_combo_phy.o \ > intel_connector.o \ > intel_display.o \ > intel_dpio_phy.o \ > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index 2a88a7eb871b..ef47cae13573 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3571,6 +3571,12 @@ void vlv_phy_pre_encoder_enable(struct > intel_encoder *encoder, > void vlv_phy_reset_lanes(struct intel_encoder *encoder, > const struct intel_crtc_state > *old_crtc_state); > =20 > +/* intel_combo_phy.c */ > +void icl_combo_phys_init(struct drm_i915_private *dev_priv); > +void icl_combo_phys_uninit(struct drm_i915_private *dev_priv); > +void cnl_combo_phys_init(struct drm_i915_private *dev_priv); > +void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv); > + > int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); > int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); > u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c > b/drivers/gpu/drm/i915/intel_combo_phy.c > new file mode 100644 > index 000000000000..8dd0a3c68f01 > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c > @@ -0,0 +1,141 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright =C2=A9 2018 Intel Corporation > + */ > + > +#include "intel_drv.h" > + > +enum { > + PROCMON_0_85V_DOT_0, > + PROCMON_0_95V_DOT_0, > + PROCMON_0_95V_DOT_1, > + PROCMON_1_05V_DOT_0, > + PROCMON_1_05V_DOT_1, > +}; > + > +static const struct cnl_procmon { > + u32 dw1, dw9, dw10; > +} cnl_procmon_values[] =3D { > + [PROCMON_0_85V_DOT_0] =3D > + { .dw1 =3D 0x00000000, .dw9 =3D 0x62AB67BB, .dw10 =3D > 0x51914F96, }, > + [PROCMON_0_95V_DOT_0] =3D > + { .dw1 =3D 0x00000000, .dw9 =3D 0x86E172C7, .dw10 =3D > 0x77CA5EAB, }, > + [PROCMON_0_95V_DOT_1] =3D > + { .dw1 =3D 0x00000000, .dw9 =3D 0x93F87FE1, .dw10 =3D > 0x8AE871C5, }, > + [PROCMON_1_05V_DOT_0] =3D > + { .dw1 =3D 0x00000000, .dw9 =3D 0x98FA82DD, .dw10 =3D > 0x89E46DC1, }, > + [PROCMON_1_05V_DOT_1] =3D > + { .dw1 =3D 0x00440000, .dw9 =3D 0x9A00AB25, .dw10 =3D > 0x8AE38FF1, }, > +}; > + > +/* > + * CNL has just one set of registers, while ICL has two sets: one > for port A and > + * the other for port B. The CNL registers are equivalent to the ICL > port A > + * registers, that's why we call the ICL macros even though the > function has CNL > + * on its name. > + */ > +static void cnl_set_procmon_ref_values(struct drm_i915_private > *dev_priv, > + enum port port) > +{ > + const struct cnl_procmon *procmon; > + u32 val; > + > + val =3D I915_READ(ICL_PORT_COMP_DW3(port)); > + switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { > + default: > + MISSING_CASE(val); > + /* fall through */ > + case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: > + procmon =3D &cnl_procmon_values[PROCMON_0_85V_DOT_0]; > + break; > + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: > + procmon =3D &cnl_procmon_values[PROCMON_0_95V_DOT_0]; > + break; > + case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: > + procmon =3D &cnl_procmon_values[PROCMON_0_95V_DOT_1]; > + break; > + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: > + procmon =3D &cnl_procmon_values[PROCMON_1_05V_DOT_0]; > + break; > + case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: > + procmon =3D &cnl_procmon_values[PROCMON_1_05V_DOT_1]; > + break; > + } > + > + val =3D I915_READ(ICL_PORT_COMP_DW1(port)); > + val &=3D ~((0xff << 16) | 0xff); > + val |=3D procmon->dw1; > + I915_WRITE(ICL_PORT_COMP_DW1(port), val); > + > + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); > + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); > +} > + > +void cnl_combo_phys_init(struct drm_i915_private *dev_priv) > +{ > + u32 val; > + > + val =3D I915_READ(CHICKEN_MISC_2); > + val &=3D ~CNL_COMP_PWR_DOWN; > + I915_WRITE(CHICKEN_MISC_2, val); > + > + /* Dummy PORT_A to get the correct CNL register from the ICL > macro */ > + cnl_set_procmon_ref_values(dev_priv, PORT_A); > + > + val =3D I915_READ(CNL_PORT_COMP_DW0); > + val |=3D COMP_INIT; > + I915_WRITE(CNL_PORT_COMP_DW0, val); > + > + val =3D I915_READ(CNL_PORT_CL1CM_DW5); > + val |=3D CL_POWER_DOWN_ENABLE; > + I915_WRITE(CNL_PORT_CL1CM_DW5, val); > +} > + > +void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) > +{ > + u32 val; > + > + val =3D I915_READ(CHICKEN_MISC_2); > + val |=3D CNL_COMP_PWR_DOWN; > + I915_WRITE(CHICKEN_MISC_2, val); > +} > + > +void icl_combo_phys_init(struct drm_i915_private *dev_priv) > +{ > + enum port port; > + > + for (port =3D PORT_A; port <=3D PORT_B; port++) { > + u32 val; > + > + val =3D I915_READ(ICL_PHY_MISC(port)); > + val &=3D ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > + I915_WRITE(ICL_PHY_MISC(port), val); > + > + cnl_set_procmon_ref_values(dev_priv, port); > + > + val =3D I915_READ(ICL_PORT_COMP_DW0(port)); > + val |=3D COMP_INIT; > + I915_WRITE(ICL_PORT_COMP_DW0(port), val); > + > + val =3D I915_READ(ICL_PORT_CL_DW5(port)); > + val |=3D CL_POWER_DOWN_ENABLE; > + I915_WRITE(ICL_PORT_CL_DW5(port), val); > + } > +} > + > +void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) > +{ > + enum port port; > + > + for (port =3D PORT_A; port <=3D PORT_B; port++) { > + u32 val; > + > + val =3D I915_READ(ICL_PHY_MISC(port)); > + val |=3D ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > + I915_WRITE(ICL_PHY_MISC(port), val); > + > + val =3D I915_READ(ICL_PORT_COMP_DW0(port)); > + val &=3D ~COMP_INIT; > + I915_WRITE(ICL_PORT_COMP_DW0(port), val); > + } > +} > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index a7eea8423580..f8da471e81aa 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3436,99 +3436,18 @@ void bxt_display_core_uninit(struct > drm_i915_private *dev_priv) > usleep_range(10, 30); /* 10 us delay per Bspec */ > } > =20 > -enum { > - PROCMON_0_85V_DOT_0, > - PROCMON_0_95V_DOT_0, > - PROCMON_0_95V_DOT_1, > - PROCMON_1_05V_DOT_0, > - PROCMON_1_05V_DOT_1, > -}; > - > -static const struct cnl_procmon { > - u32 dw1, dw9, dw10; > -} cnl_procmon_values[] =3D { > - [PROCMON_0_85V_DOT_0] =3D > - { .dw1 =3D 0x00000000, .dw9 =3D 0x62AB67BB, .dw10 =3D > 0x51914F96, }, > - [PROCMON_0_95V_DOT_0] =3D > - { .dw1 =3D 0x00000000, .dw9 =3D 0x86E172C7, .dw10 =3D > 0x77CA5EAB, }, > - [PROCMON_0_95V_DOT_1] =3D > - { .dw1 =3D 0x00000000, .dw9 =3D 0x93F87FE1, .dw10 =3D > 0x8AE871C5, }, > - [PROCMON_1_05V_DOT_0] =3D > - { .dw1 =3D 0x00000000, .dw9 =3D 0x98FA82DD, .dw10 =3D > 0x89E46DC1, }, > - [PROCMON_1_05V_DOT_1] =3D > - { .dw1 =3D 0x00440000, .dw9 =3D 0x9A00AB25, .dw10 =3D > 0x8AE38FF1, }, > -}; > - > -/* > - * CNL has just one set of registers, while ICL has two sets: one > for port A and > - * the other for port B. The CNL registers are equivalent to the ICL > port A > - * registers, that's why we call the ICL macros even though the > function has CNL > - * on its name. > - */ > -static void cnl_set_procmon_ref_values(struct drm_i915_private > *dev_priv, > - enum port port) > -{ > - const struct cnl_procmon *procmon; > - u32 val; > - > - val =3D I915_READ(ICL_PORT_COMP_DW3(port)); > - switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { > - default: > - MISSING_CASE(val); > - /* fall through */ > - case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: > - procmon =3D &cnl_procmon_values[PROCMON_0_85V_DOT_0]; > - break; > - case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: > - procmon =3D &cnl_procmon_values[PROCMON_0_95V_DOT_0]; > - break; > - case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: > - procmon =3D &cnl_procmon_values[PROCMON_0_95V_DOT_1]; > - break; > - case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: > - procmon =3D &cnl_procmon_values[PROCMON_1_05V_DOT_0]; > - break; > - case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: > - procmon =3D &cnl_procmon_values[PROCMON_1_05V_DOT_1]; > - break; > - } > - > - val =3D I915_READ(ICL_PORT_COMP_DW1(port)); > - val &=3D ~((0xff << 16) | 0xff); > - val |=3D procmon->dw1; > - I915_WRITE(ICL_PORT_COMP_DW1(port), val); > - > - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); > - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); > -} > - > static void cnl_display_core_init(struct drm_i915_private *dev_priv, > bool resume) > { > struct i915_power_domains *power_domains =3D &dev_priv- > >power_domains; > struct i915_power_well *well; > - u32 val; > =20 > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > =20 > /* 1. Enable PCH Reset Handshake */ > intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); > =20 > - /* 2. Enable Comp */ > - val =3D I915_READ(CHICKEN_MISC_2); > - val &=3D ~CNL_COMP_PWR_DOWN; > - I915_WRITE(CHICKEN_MISC_2, val); > - > - /* Dummy PORT_A to get the correct CNL register from the ICL > macro */ > - cnl_set_procmon_ref_values(dev_priv, PORT_A); > - > - val =3D I915_READ(CNL_PORT_COMP_DW0); > - val |=3D COMP_INIT; > - I915_WRITE(CNL_PORT_COMP_DW0, val); > - > - /* 3. */ > - val =3D I915_READ(CNL_PORT_CL1CM_DW5); > - val |=3D CL_POWER_DOWN_ENABLE; > - I915_WRITE(CNL_PORT_CL1CM_DW5, val); > + /* 2-3. */ > + cnl_combo_phys_init(dev_priv); > =20 > /* > * 4. Enable Power Well 1 (PG1). > @@ -3553,7 +3472,6 @@ static void cnl_display_core_uninit(struct > drm_i915_private *dev_priv) > { > struct i915_power_domains *power_domains =3D &dev_priv- > >power_domains; > struct i915_power_well *well; > - u32 val; > =20 > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > =20 > @@ -3577,10 +3495,8 @@ static void cnl_display_core_uninit(struct > drm_i915_private *dev_priv) > =20 > usleep_range(10, 30); /* 10 us delay per Bspec */ > =20 > - /* 5. Disable Comp */ > - val =3D I915_READ(CHICKEN_MISC_2); > - val |=3D CNL_COMP_PWR_DOWN; > - I915_WRITE(CHICKEN_MISC_2, val); > + /* 5. */ > + cnl_combo_phys_uninit(dev_priv); > } > =20 > void icl_display_core_init(struct drm_i915_private *dev_priv, > @@ -3588,31 +3504,14 @@ void icl_display_core_init(struct > drm_i915_private *dev_priv, > { > struct i915_power_domains *power_domains =3D &dev_priv- > >power_domains; > struct i915_power_well *well; > - enum port port; > - u32 val; > =20 > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > =20 > /* 1. Enable PCH reset handshake. */ > intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); > =20 > - for (port =3D PORT_A; port <=3D PORT_B; port++) { > - /* 2. Enable DDI combo PHY comp. */ > - val =3D I915_READ(ICL_PHY_MISC(port)); > - val &=3D ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > - I915_WRITE(ICL_PHY_MISC(port), val); > - > - cnl_set_procmon_ref_values(dev_priv, port); > - > - val =3D I915_READ(ICL_PORT_COMP_DW0(port)); > - val |=3D COMP_INIT; > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > - > - /* 3. Set power down enable. */ > - val =3D I915_READ(ICL_PORT_CL_DW5(port)); > - val |=3D CL_POWER_DOWN_ENABLE; > - I915_WRITE(ICL_PORT_CL_DW5(port), val); > - } > + /* 2-3. */ > + icl_combo_phys_init(dev_priv); > =20 > /* > * 4. Enable Power Well 1 (PG1). > @@ -3640,8 +3539,6 @@ void icl_display_core_uninit(struct > drm_i915_private *dev_priv) > { > struct i915_power_domains *power_domains =3D &dev_priv- > >power_domains; > struct i915_power_well *well; > - enum port port; > - u32 val; > =20 > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > =20 > @@ -3663,16 +3560,8 @@ void icl_display_core_uninit(struct > drm_i915_private *dev_priv) > intel_power_well_disable(dev_priv, well); > mutex_unlock(&power_domains->lock); > =20 > - /* 5. Disable Comp */ > - for (port =3D PORT_A; port <=3D PORT_B; port++) { > - val =3D I915_READ(ICL_PHY_MISC(port)); > - val |=3D ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > - I915_WRITE(ICL_PHY_MISC(port), val); > - > - val =3D I915_READ(ICL_PORT_COMP_DW0(port)); > - val &=3D ~COMP_INIT; > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > - } > + /* 5. */ > + icl_combo_phys_uninit(dev_priv); > } > =20 > static void chv_phy_control_init(struct drm_i915_private *dev_priv) --=-6KW09arE5kxOLZucBoUp Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEyBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlvjTeMACgkQVenbO/mO Wkmg2gf4sXk5WKam7ybR1j3rL4l+2u0ddO+7SrYGqFWh1K4DkV9typnI7sv0NeZ0 7vcmTt5UX4ocT0gjAZdOXD8Ccjt6DFp1aypJ2vzGVQybUrnEGcFjit+pG7qX3czR dI9io3ZqpOjnU9kW5HI71i4o3UVOhSNV0+eY8z6rMS5aU1cFoeO01QEUisucnxq1 dI9t8VLvYdiPXULIpmh2QqHfxz9CsWgyqXFIDi9dQ7JXcWLS6lAis6NmppmlrdIW ZVGdc1TOKFydgaA073cRVC5AisMUXQRSt0JrMXhjQt4PP1dPBYvhoH+4neckAV3a 37QKBWElaT9UA+7uSuGi+2MtKZqk =uIOY -----END PGP SIGNATURE----- --=-6KW09arE5kxOLZucBoUp-- --===============2091536211== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============2091536211==--