From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C845C433FE for ; Fri, 14 Oct 2022 10:58:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5585110E084; Fri, 14 Oct 2022 10:58:26 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08EEE10E9D9; Fri, 14 Oct 2022 10:58:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665745099; x=1697281099; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=8WHP7256XgL6r+GHZnM4u3uombJFm6QP9tixwB4AJ5U=; b=nvlq0pMpNSTvMXkEmDiMAt1QlOiNQoUAji6c10Ai187Ptt89JhcPF/37 rTuqwP4xbehux4YYkbkVy8H8wy/+Gs6UTN/IJG7ThKEOR3CN/YCcFJBgh 9CaxcXzwreWbk1fmbtEJxbTsuN3eBN7IVGr7z8X5aCMRBYbDvYj4X855k ox1/wMKCaCxLz7B2xjxEn3nwSaYAz8lNfR/Ncl0LIvJOzS5ESYMF7D6uW SoYURRClkRtWiBmVUMN5j9fwik0tsxYX/U2tC7jbaHP2mnezElkYo6HBf Gz+jhzmOvroE82u9e6H/sgeGdg02JS5102c1J/lopf6PYuPmXmFMnYiCD Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="285737545" X-IronPort-AV: E=Sophos;i="5.95,184,1661842800"; d="scan'208";a="285737545" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 03:58:16 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="629899238" X-IronPort-AV: E=Sophos;i="5.95,184,1661842800"; d="scan'208";a="629899238" Received: from salamu-mobl1.ger.corp.intel.com (HELO [10.252.11.69]) ([10.252.11.69]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 03:58:14 -0700 Message-ID: <466153a3-59ef-e91f-d267-ff9c777eccb9@intel.com> Date: Fri, 14 Oct 2022 11:58:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.3.1 Content-Language: en-GB To: Jordan Justen , intel-gfx@lists.freedesktop.org References: <20221004114915.221708-1-matthew.auld@intel.com> <20221004114915.221708-2-matthew.auld@intel.com> <166573205234.1044993.5297661838478296333@jljusten-skl.local> From: Matthew Auld In-Reply-To: <166573205234.1044993.5297661838478296333@jljusten-skl.local> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= , Michal Mrozek , dri-devel@lists.freedesktop.org, Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 14/10/2022 08:20, Jordan Justen wrote: > Acked-by: Jordan Justen Thanks. Can I take that as ack for merging the series from Mesa POV? I think Lionel was going to test this, but I think keeps getting swamped with other stuff. We kind of urgently need to land this series. > > On 2022-10-04 04:49:15, Matthew Auld wrote: >> On some platforms we potentially have different alignment restrictions >> depending on the memory type. We also now have different alignment >> restrictions for the same region across different kernel versions. >> Extend the region query to return the minimum required GTT alignment. >> >> Testcase: igt@gem_create@create-ext-placement-alignment >> Testcase: igt@i915_query@query-regions-sanity-check >> Suggested-by: Lionel Landwerlin >> Signed-off-by: Matthew Auld >> Cc: Michal Mrozek >> Cc: Thomas Hellström >> Cc: Stuart Summers >> Cc: Jordan Justen >> Cc: Yang A Shi >> Cc: Nirmoy Das >> Cc: Niranjana Vishwanathapura >> --- >> drivers/gpu/drm/i915/i915_query.c | 1 + >> include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++++++++-- >> 2 files changed, 28 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c >> index 6ec9c9fb7b0d..111377f210ed 100644 >> --- a/drivers/gpu/drm/i915/i915_query.c >> +++ b/drivers/gpu/drm/i915/i915_query.c >> @@ -498,6 +498,7 @@ static int query_memregion_info(struct drm_i915_private *i915, >> info.region.memory_class = mr->type; >> info.region.memory_instance = mr->instance; >> info.probed_size = mr->total; >> + info.gtt_alignment = mr->min_page_size; >> >> if (mr->type == INTEL_MEMORY_LOCAL) >> info.probed_cpu_visible_size = mr->io_size; >> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >> index 08d69e36fb66..2e613109356b 100644 >> --- a/include/uapi/drm/i915_drm.h >> +++ b/include/uapi/drm/i915_drm.h >> @@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info { >> /** @region: The class:instance pair encoding */ >> struct drm_i915_gem_memory_class_instance region; >> >> - /** @rsvd0: MBZ */ >> - __u32 rsvd0; >> + union { >> + /** @rsvd0: MBZ */ >> + __u32 rsvd0; >> + /** >> + * @gtt_alignment: >> + * >> + * The minimum required GTT alignment for this type of memory. >> + * When allocating a GTT address it must be aligned to this >> + * value or larger. On some platforms the kernel might opt to >> + * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT >> + * pages can then be used if we also use 64K GTT alignment. >> + * >> + * NOTE: If this is zero then this must be an older >> + * kernel which lacks support for this field. >> + * >> + * Side note: For larger objects (especially for >> + * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should >> + * consider potentially bumping the GTT alignment to say 2M, >> + * which could potentially increase the likelihood of the kernel >> + * being able to utilise 2M GTT pages underneath, if the layout >> + * of the physical pages allows it. On some configurations we >> + * can then also use a more efficient page-table layout, if we >> + * can't use the more desirable 2M GTT page, so long as we know >> + * that the entire page-table will be used by this object. >> + */ >> + __u32 gtt_alignment; >> + }; >> >> /** >> * @probed_size: Memory probed by the driver >> -- >> 2.37.3 >>