Re: [PATCH] dri: Do not tile stencil buffer

[Kenneth Graunke <kenneth@whitecape.org>]

On 07/18/2011 05:08 PM, Chad Versace wrote:
> Until now, the stencil buffer was allocated as a Y tiled buffer, because
> in several locations the PRM states that it is. However, it is actually
> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
> 4.5.2.1 W-Major Format:
>     W-Major Tile Format is used for separate stencil.
> 
> The GTT is incapable of W fencing, so we allocate the stencil buffer with
> I915_TILING_NONE and decode the tile's layout in software.
> 
> This commit mutually depends on the mesa commit:
>     intel: Fix stencil buffer to be W tiled
>     Author: Chad Versace <chad@chad-versace.us>
>     Date:   Mon Jul 18 00:37:45 2011 -0700
> 
> CC: Eric Anholt <eric@anholt.net>
> CC: Kenneth Graunke <kenneth@whitecape.org>
> CC: Ian Romancik <ian.d.romanick@intel.com>
> Signed-off-by: Chad Versace <chad@chad-versace.us>
> ---
>  src/intel_dri.c |   16 ++++++++++++----
>  1 files changed, 12 insertions(+), 4 deletions(-)

For the series:
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

(I would say Reviewed-by, but I haven't verified the math.  That said, I
don't think I need to...I've seen how rigorously you investigated this.)

Happy to see these go in whenever.  We definitely need them in 7.11 and
2.16.