From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adam Jackson Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places Date: Wed, 02 Nov 2011 17:16:39 -0400 Message-ID: <4EB1B337.1090501@redhat.com> References: <1320214830-12696-1-git-send-email-keithp@keithp.com> <1320214830-12696-4-git-send-email-keithp@keithp.com> <20111102092019.3a635632@jbarnes-desktop> <4EB17A50.6050804@redhat.com> <4EB19BB4.6030505@redhat.com> <4EB1A9A7.8070900@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Keith Packard Cc: Jesse Barnes , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 11/2/11 5:13 PM, Keith Packard wrote: > On Wed, 02 Nov 2011 16:35:51 -0400, Adam Jackson wrote: > >> It is? The DP 1.1a text for lane count is "For Rev.1.1, only the >> following three values are supported. All other values are reserved." > > Yeah, if you look at the MAX_LINK_RATE field, we assume that it has a > useful value. I'll bet they were thinking of letting the spec support > things like alternate clock rates or 3 lanes or something, and the 1.1 > version just tied things down to allow only sensible values there. > > How about we just always use the DPCD value? Looks good. Reviewed-by: Adam Jackson - ajax