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From: Shobhit Kumar <shobhit.kumar@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Beeresh G <beeresh.g@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 11/25] drm/i915: Enable HDMI on ValleyView
Date: Mon, 26 Mar 2012 08:51:37 +0530	[thread overview]
Message-ID: <4F6FE0C1.30001@intel.com> (raw)
In-Reply-To: <20120321210247.GD9913@phenom.ffwll.local>

On Thursday 22 March 2012 02:32 AM, Daniel Vetter wrote:
> On Wed, Mar 21, 2012 at 12:48:32PM -0700, Jesse Barnes wrote:
>> From: Shobhit Kumar<shobhit.kumar@intel.com>
>>
>> HDMI register offsets are different in Valleyview. Add support for the
>> same.
>>
>> Signed-off-by: Beeresh G<beeresh.g@intel.com>
>> Signed-off-by: Shobhit Kumar<shobhit.kumar@intel.com>
>> Reviewed-by: Vijay Purushothaman<vijay.a.purushothaman@intel.com>
>> Reviewed-by: Jesse Barnes<jesse.barnes@intel.com>
>> Signed-off-by: Jesse Barnes<jbarnes@virtuousgeek.org>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h   |   16 +++++++++++++++
>>   drivers/gpu/drm/i915/intel_hdmi.c |   39 ++++++++++++++++++++++++++++++++++++-
>>   2 files changed, 54 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c187398..f04bfbf 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3452,6 +3452,21 @@
>>   #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>>   #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>>
>> +#define VLV_VIDEO_DIP_CTL_A		0x60220
>> +#define VLV_VIDEO_DIP_DATA_A		0x60208
>> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
>> +
>> +#define VLV_VIDEO_DIP_CTL_B		0x61170
>> +#define VLV_VIDEO_DIP_DATA_B		0x61174
>> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
>> +
>> +#define VLV_TVIDEO_DIP_CTL(pipe) \
>> +	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
>> +#define VLV_TVIDEO_DIP_DATA(pipe) \
>> +	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
>> +#define VLV_TVIDEO_DIP_GCP(pipe) \
>> +	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
>> +
>>   #define _TRANS_HTOTAL_B          0xe1000
>>   #define _TRANS_HBLANK_B          0xe1004
>>   #define _TRANS_HSYNC_B           0xe1008
>> @@ -3672,6 +3687,7 @@
>>   #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
>>
>>   /* or SDVOB */
>> +#define VLV_HDMIB 0x61140
>>   #define HDMIB   0xe1140
>>   #define  PORT_ENABLE    (1<<  31)
>>   #define  TRANSCODER(pipe)       ((pipe)<<  30)
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index cae3e5f..3f4a2d2 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -177,6 +177,37 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
>>
>>   	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>>   }
>> +
>> +static void vlv_write_infoframe(struct drm_encoder *encoder,
>> +				     struct dip_infoframe *frame)
>> +{
>> +	uint32_t *data = (uint32_t *)frame;
>> +	struct drm_device *dev = encoder->dev;
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	struct drm_crtc *crtc = encoder->crtc;
>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>> +	unsigned i, len = DIP_HEADER_SIZE + frame->len;
>> +	u32 flags, val = I915_READ(reg);
>> +
>> +	intel_wait_for_vblank(dev, intel_crtc->pipe);
>> +
>> +	flags = intel_infoframe_index(frame);
>> +
>> +	val&= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
>> +
>> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>> +
>> +	for (i = 0; i<  len; i += 4) {
>> +		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
>> +		data++;
>> +	}
>> +
>> +	flags |= intel_infoframe_flags(frame);
>> +
>> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>> +}
>> +
>>   static void intel_set_infoframe(struct drm_encoder *encoder,
>>   				struct dip_infoframe *frame)
>>   {
>> @@ -522,10 +553,12 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
>>   	intel_encoder->crtc_mask = (1<<  0) | (1<<  1) | (1<<  2);
>>
>>   	/* Set up the DDC bus. */
>> +	/* For VLV SDVOB == HDMIB */
>>   	if (sdvox_reg == SDVOB) {
>>   		intel_encoder->clone_mask = (1<<  INTEL_HDMIB_CLONE_BIT);
>>   		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
>>   		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
>> +	/* For VLV SDVOC == HDMIC */
> I'm a bit confused about these two comments here. Afaict the code already
> works that way, not just on vlv. Can we just drop this hunk?
Yes we should drop this. Just couple of informational comments which I 
missed to remove.

Regards
Shobhit

  reply	other threads:[~2012-03-26  3:21 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-21 19:48 [RFC] ValleyView support Jesse Barnes
2012-03-21 19:48 ` [PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c Jesse Barnes
2012-03-21 20:40   ` Eugeni Dodonov
2012-03-21 19:48 ` [PATCH 02/25] drm/i915: add debug message when EDID fetch fails Jesse Barnes
2012-03-21 20:44   ` Eugeni Dodonov
2012-03-21 20:53     ` Jesse Barnes
2012-03-22  1:02       ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 03/25] drm/i915: re-order GT IIR bit definitions Jesse Barnes
2012-03-22  1:10   ` Ben Widawsky
2012-03-22 18:40     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block Jesse Barnes
2012-03-22  1:30   ` Ben Widawsky
2012-03-22 15:45     ` Jesse Barnes
2012-03-22 16:11       ` Ben Widawsky
2012-03-22 17:00         ` Jesse Barnes
2012-03-26 18:52           ` Rodrigo Vivi
2012-03-21 19:48 ` [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView Jesse Barnes
2012-03-22  1:39   ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support Jesse Barnes
2012-03-21 20:52   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set Jesse Barnes
2012-03-21 20:55   ` Daniel Vetter
2012-03-21 21:29     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-03-22  1:53   ` Ben Widawsky
2012-03-22 15:03     ` Purushothaman, Vijay A
2012-03-21 19:48 ` [PATCH 09/25] drm/915: program driain latency regs on ValleyView Jesse Barnes
2012-03-21 21:00   ` Daniel Vetter
2012-03-21 21:52     ` Adam Jackson
2012-03-21 19:48 ` [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-03-22 18:31   ` Ben Widawsky
2012-03-21 19:48 ` [PATCH 11/25] drm/i915: Enable HDMI on ValleyView Jesse Barnes
2012-03-21 21:02   ` Daniel Vetter
2012-03-26  3:21     ` Shobhit Kumar [this message]
2012-03-21 19:48 ` [PATCH 12/25] agp/intel: map more registers for use by the GTT code Jesse Barnes
2012-03-21 21:04   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function Jesse Barnes
2012-03-21 21:07   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 14/25] agp/intel: always use uncached mappings on VLV Jesse Barnes
2012-03-21 21:09   ` Daniel Vetter
2012-03-21 21:23     ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 15/25] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-03-21 19:48 ` [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions Jesse Barnes
2012-03-21 21:11   ` Daniel Vetter
2012-03-21 21:32     ` Jesse Barnes
2012-03-21 21:55       ` Adam Jackson
2012-03-21 22:11         ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 17/25] drm/i915: ValleyView cacheability is different Jesse Barnes
2012-03-21 21:19   ` Daniel Vetter
2012-03-21 21:35     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 18/25] drm/i915: ValleyView IRQ support Jesse Barnes
2012-03-21 19:48 ` [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView Jesse Barnes
2012-03-21 21:33   ` Daniel Vetter
2012-03-21 21:36     ` Jesse Barnes
2012-03-22 21:13       ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 20/25] drm/i915: check for disabled interrupts " Jesse Barnes
2012-03-21 19:48 ` [PATCH 21/25] drm/i915: add HDMI and DP port enumeration " Jesse Barnes
2012-03-21 19:48 ` [PATCH 22/25] drm/i915: remove some unneeded debug messages Jesse Barnes
2012-03-21 21:36   ` Daniel Vetter
2012-03-21 21:39     ` Daniel Vetter
2012-03-21 21:55     ` Jesse Barnes
2012-03-21 19:48 ` [PATCH 23/25] drm/i915: add ValleyView clock gating init Jesse Barnes
2012-03-21 21:40   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct Jesse Barnes
2012-03-21 21:43   ` Daniel Vetter
2012-03-21 19:48 ` [PATCH 25/25] drm/i915: don't write ring regs until they're set up Jesse Barnes
2012-03-21 21:46   ` Daniel Vetter
2012-03-21 21:56     ` Jesse Barnes
2012-03-21 21:54 ` [RFC] ValleyView support Daniel Vetter

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