From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: Re: [PATCH] drm/i915: properly enable the blc controller on the right pipe Date: Tue, 12 Jun 2012 12:15:22 -0300 Message-ID: <4FD75D0A.7050009@linux.intel.com> References: <20120605111529.GB4704@phenom.ffwll.local> <1338891294-11845-1-git-send-email-daniel.vetter@ffwll.ch> Reply-To: eugeni.dodonov@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 903C79ED7B for ; Tue, 12 Jun 2012 08:13:51 -0700 (PDT) In-Reply-To: <1338891294-11845-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On 06/05/2012 07:14 AM, Daniel Vetter wrote: > + /* Note that this can also get called through dpms changes. And > + * we don't track the backlight dpms state, hence check whether > + * we have to do anything first. */ > + if (tmp & BLM_PWM_ENABLE) > + return; > + I am tempted to add a WARN_ON(pipe > dev_priv->num_pipe) here, now that we should handle 3 pipes. > + if (dev_priv->num_pipe == 3) > + tmp &= ~BLM_PIPE_SELECT_IVB; > + else > + tmp &= ~BLM_PIPE_SELECT; > + > + tmp |= BLM_PIPE(pipe); > + tmp &= ~BLM_PWM_ENABLE; > + > + I915_WRITE(reg, tmp); > + POSTING_READ(reg); > + I915_WRITE(reg, tmp | BLM_PWM_ENABLE); > + } But besides that: Reviewed-by: Eugeni Dodonov Eugeni