[Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+

Ville Syrjala
2021-10-06T20:49:45Z

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the generic link training code should be in check now.
Let's move on to actually programming the each TX lane with
its own individual settings.

Ville Syrjälä (16):
drm/i915: Remove pointless extra namespace from dkl/snps buf trans
structs
drm/i915: Shrink {icl_mg,tgl_dkl}_phy_ddi_buf_trans
drm/i915: Use standard form terminating condition for lane for loops
drm/i915: Add all per-lane register definitions for icl combo phy
drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
drm/i915: Extract icl_combo_phy_loadgen_select()
drm/i915: Stop using group access when progrmming icl combo phy TX
drm/i915: Query the vswing levels per-lane for icl combo phy
drm/i915: Query the vswing levels per-lane for icl mg phy
drm/i915: Query the vswing levels per-lane for tgl dkl phy
drm/i915: Query the vswing levels per-lane for snps phy
drm/i915: Enable per-lane drive settings for icl+
drm/i915: Use intel_de_rmw() for tgl dkl phy programming
drm/i915: Use intel_de_rmw() for icl mg phy programming
drm/i915: Use intel_de_rmw() for icl combo phy programming
drm/i915: Fix icl+ combo phy static lane power down setup

drivers/gpu/drm/i915/display/icl_dsi.c | 14 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 10 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 265 ++++++++----------
.../drm/i915/display/intel_ddi_buf_trans.h | 18 +-
.../drm/i915/display/intel_dp_link_training.c | 5 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 11 +-
7 files changed, 154 insertions(+), 177 deletions(-)

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2.32.0