From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kenneth Graunke <kenneth@whitecape.org>
Subject: Re: [PATCH 3/4] drm/i915: set proper DPIO post divider
 for VGA on VLV v4
Date: Mon, 06 May 2013 10:52:36 -0700
Message-ID: <5187EDE4.2090501@whitecape.org>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
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List-Id: intel-gfx@lists.freedesktop.org

On 05/02/2013 10:48 AM, Jesse Barnes wrote:
> Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
> that doesn't actually work as well as the high freq divider here in
> practice, just use the high freq divider all the time.
>
> v2: remove unconditional write (Jesse)
>      check for pixel rate properly (Jesse)
> v3: give up, the DAC divider apparently doesn't work, and low res modes
>      work ok (Jesse)
>      remove debug msg (Jesse)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

VGA is broken with today's drm-intel-next-queued (3a2128bcac1ae). 
Applying this patch fixes it.  Thanks!

Tested-by: Kenneth Graunke <kenneth@whitecape.org>

> ---
>   drivers/gpu/drm/i915/intel_display.c |   11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6504337..59c2114 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4425,10 +4425,13 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>   	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>   	mdiv |= ((bestn << DPIO_N_SHIFT));
>   	mdiv |= (1 << DPIO_K_SHIFT);
> -	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
> -	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
> -	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
> -		mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> +
> +	/*
> +	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
> +	 * but we don't support that).
> +	 * Note: don't use the DAC post divider as it seems unstable.
> +	 */
> +	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
>   	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
>
>   	mdiv |= DPIO_ENABLE_CALIBRATION;
>