From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Richter Subject: [PATCH] drm/i915: Avoid flicker with horizontal panning on 830GM Date: Sun, 01 Sep 2013 19:01:49 +0200 Message-ID: <522372FD.5080001@math.tu-berlin.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from charon.rus.uni-stuttgart.de (charon.rus.uni-stuttgart.de [129.69.192.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0128E66F1 for ; Sun, 1 Sep 2013 10:02:11 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: daniel.vetter@ffwll.ch List-Id: intel-gfx@lists.freedesktop.org Dear intel-gfx developers, When panning is enabled on the 830GM, horizontal panning creates a lot of flickering on specific pixel positions. After testing, I found that the reason for this is that panning works by altering the frame origin pointer, which, however, has certain alignment restrictions. If the pointer is not aligned correctly, the screen starts to flicker as, probably, DMA fails. The following patch against drm/i915/intel_display.c fixes the issue by ensuring correct alignment. As result, horizontal panning works correctly, but is a bit "jumpy". Unclear whether the problem affects any other chipset revisions, thus the patch is currently only enabled for rev.2. Greetings, Thomas diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bcb62fe..8304e30 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1987,8 +1987,13 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, I915_WRITE(reg, dspcntr); - linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - + if (INTEL_INFO(dev)->gen > 2) { + linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); + } else { + /* align the linear offset to 64 pixel boundaries */ + linear_offset = y * fb->pitches[0] + (x & -32) * (fb->bits_per_pixel / 8); + } + if (INTEL_INFO(dev)->gen >= 4) { intel_crtc->dspaddr_offset = intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,