From: Thomas Richter <thor@math.tu-berlin.de>
To: Daniel Vetter <daniel@ffwll.ch>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Questions on display pipes on 835GM
Date: Sat, 05 Oct 2013 10:33:44 +0200 [thread overview]
Message-ID: <524FCEE8.4010307@math.tu-berlin.de> (raw)
In-Reply-To: <29427_1378101775_52242A0E_29427_747_1_20130902060151.GE9374@phenom.ffwll.local>
Hi Daniel, hi folks,
just playing again with the support code for the NS2501 DVO in my old
laptop. Despite finding one bug I'll send a patch
for soon, there is something else that makes we wonder, and that is the
connection to external monitors.
Just to remind you, the NS2501 in this specific laptop, or probably in
general, seems to be clocked by parts of the
sync signal of the display pipe. If the display pipe does not deliver
the right clock, the DVO locks up and does not
react anymore to any commands on the i2c bus. The current ns2501 DVO
driver code thus includes a little hack that,
if it detects that the DVO remains silent, forces the pipe A DLL to the
right values to reactivate it. This is a hack, though
it works.
Now, interesting things happen if I connect an external monitor: The
i915 code reads the edid data from the monitor,
finds that the monitor prefers a high clock rate (here an old CRT) of
75Hz vertical, and reconfigures the display pipe.
Interestingly, this *also* seems to modify the display pipe of the DVO
which should actually be connected to a
different pipe. Anyhow, as now the DVO sees a clock signal out of its
operating range (60Hz vertical) it locks up and
no display appears *on the internal* LCD. In fact, the display breaks
down completely and all you get is a residual
display on the TFT which no longer receives refresh. If I force the
clocking of the external monitor to 60Hz, both
displays work again. So for me it looks like the role of the display
pipes is somehow swapped if I connect an external
monitor - it seems as if in this case either both monitors are driven by
the same pipe (why?) of that now pipe B feeds
the DVI1 hence the DVO and the TFT, and pipe A feeds the external monitor.
Thus, here my questions:
*) Can I, within the dvo driver code, somehow detect to which display
pipe the DVO and thus the TFT is actually connected
to?
*) Can I somehow prohibit that the DVO is driven by *anything but* the
60Hz signal it likes, thus to prevent the lock-up
and disable the weird hack I'm currently using?
Somehow, the logic which display pipe drives which output is still
unclear to me. Would be great if somebody could help
me out here.
Thanks,
Thomas
next prev parent reply other threads:[~2013-10-05 8:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-23 22:51 [PATCH] drm/i915: enable trickle feed on Haswell Paulo Zanoni
2013-08-30 17:25 ` Ville Syrjälä
2013-09-02 6:01 ` Daniel Vetter
[not found] ` <29427_1378101775_52242A0E_29427_747_1_20130902060151.GE9374@phenom.ffwll.local>
2013-10-05 8:33 ` Thomas Richter [this message]
2013-10-05 11:44 ` Questions on display pipes on 835GM Ville Syrjälä
[not found] ` <29761_1380973482_524FFBA9_29761_4042_1_20131005114432.GE9395@intel.com>
2013-10-05 16:47 ` Thomas Richter
2013-10-05 19:24 ` Daniel Vetter
2013-10-05 19:39 ` Daniel Vetter
[not found] ` <29761_1381001928_52506AC8_29761_5606_1_20131005193904.GX31334@phenom.ffwll.local>
2013-10-05 23:09 ` Thomas Richter
2013-10-05 23:37 ` Daniel Vetter
[not found] ` <5132_1381149082_5252A99A_5132_80_1_CAKMK7uHkOJ=urFKCacocf_i+6YL9Azf5vK=Au-kRJMi=sNBP1Q@mail.gmail.com>
2013-10-07 21:58 ` Broken in 3.10.10 (was: Questions on display pipes on 835GM) Thomas Richter
2013-10-08 7:24 ` Daniel Vetter
2013-10-08 8:39 ` Daniel Vetter
2013-10-08 9:14 ` Chris Wilson
[not found] ` <26192_1381221546_5253C4A9_26192_7222_1_CAKMK7uGvk9vuNXunutyHjkGjvBWsv7ObN02EfbG2679MtQ5M=A@mail.gmail.com>
2013-10-08 17:06 ` Broken in 3.10.10 Thomas Richter
2013-10-05 23:04 ` [PATCH] 835GM DLL setup Thomas Richter
2013-10-05 23:46 ` Daniel Vetter
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