From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Richter <thor@math.tu-berlin.de>
Subject: Re: Questions on display pipes on 835GM
Date: Sun, 06 Oct 2013 01:09:49 +0200
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To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
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Hi Daniel,

> btw I've just read through your dvo code again and I think we can fix this
> easier. If I read your enable hack correctly then we need to have the dpll
> running and the DVO port on. The problem now is that in the dvo ->modeset
> callback this is explicitly _not_ the case.

Please also check the latest mail (just minutes above). There seem to be 
three conditions, actually: DPLL running, DVO on, and high-speed mode 
selected *at least* if there is only one pipe active.

> This is not a big issue when there's only one pipe in use, but it wreaks
> havoc when more than one pipe is in use. So we need to move all that code
> somewhere else.

Agreed.

> Now if you follow the callchains around the dvo->dpms callbacks the DVO
> port and DPLL are always enabled at that point in time, so I think we
> should be able to fix this all by moving the modeset code around to that
> place.

True, but probably with the high-speed bit in the wrong state.

Greetings,
	Thomas