[PATCH 0/5] BDW libdrm support

[PATCH 0/5] BDW libdrm support

[Ben Widawsky]

Nothing special here... I'm fine with not pushing any of the AUB stuff if
anyone has issues.

Ben Widawsky (2):
  intel/bdw: Add broadwell chipset IDs
  intel/bdw: Handle gen8 bufmgr_init

Damien Lespiau (2):
  intel/bdw: Add gen8 to the decode init
  intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps

Kenneth Graunke (1):
  intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.

 intel/intel_bufmgr_gem.c | 24 +++++++++++++++++++-----
 intel/intel_chipset.h    | 22 +++++++++++++++++++++-
 intel/intel_decode.c     |  4 +++-
 3 files changed, 43 insertions(+), 7 deletions(-)

-- 
1.8.4.2

[PATCH 1/5] intel/bdw: Add broadwell chipset IDs

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

v2: Rename s/<SECRET>/IRIS/

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_chipset.h | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index aeb439e..e5589be 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -148,6 +148,12 @@
 #define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
 #define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
 #define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
+#define BDW_SPARE			0x2
+#define BDW_ULT				0x6
+#define BDW_SERVER			0xa
+#define BDW_IRIS			0xb
+#define BDW_WORKSTATION			0xd
+#define BDW_ULX				0xe
 
 #define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
 #define PCI_CHIP_VALLEYVIEW_1		0x0f31
@@ -296,10 +302,24 @@
 				 IS_HSW_GT2(devid) || \
 				 IS_HSW_GT3(devid))
 
+#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
+				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
+				((devid & 0x000f) == BDW_SPARE) ? 1 : \
+				((devid & 0x000f) == BDW_ULT) ? 1 : \
+				((devid & 0x000f) == BDW_IRIS) ? 1 : \
+				((devid & 0x000f) == BDW_SERVER) ? 1 : \
+				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
+				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
+
+
+#define IS_GEN8(devid)		IS_BROADWELL(devid)
+
 #define IS_9XX(dev)		(IS_GEN3(dev) || \
 				 IS_GEN4(dev) || \
 				 IS_GEN5(dev) || \
 				 IS_GEN6(dev) || \
-				 IS_GEN7(dev))
+				 IS_GEN7(dev) || \
+				 IS_GEN8(dev))
+
 
 #endif /* _INTEL_CHIPSET_H */
-- 
1.8.4.2

[PATCH 2/5] intel/bdw: Handle gen8 bufmgr_init

[Ben Widawsky]

From: Ben Widawsky <ben@bwidawsk.net>

[bwidawsk: Added Damien's SOB]
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_bufmgr_gem.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 278f5c8..32a226c 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3124,6 +3124,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 		bufmgr_gem->gen = 6;
 	else if (IS_GEN7(bufmgr_gem->pci_device))
 		bufmgr_gem->gen = 7;
+	else if (IS_GEN8(bufmgr_gem->pci_device))
+		bufmgr_gem->gen = 8;
 	else {
 		free(bufmgr_gem);
 		return NULL;
-- 
1.8.4.2

[PATCH 3/5] intel/bdw: Add gen8 to the decode init

[Ben Widawsky]

From: Damien Lespiau <damien.lespiau@intel.com>

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_decode.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 1b80b75..c0a0caf 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
 	ctx->devid = devid;
 	ctx->out = stdout;
 
-	if (IS_GEN7(devid))
+	if (IS_GEN8(devid))
+		ctx->gen = 8;
+	else if (IS_GEN7(devid))
 		ctx->gen = 7;
 	else if (IS_GEN6(devid))
 		ctx->gen = 6;
-- 
1.8.4.2

[PATCH 4/5] intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.

[Ben Widawsky]

From: Kenneth Graunke <kenneth@whitecape.org>

Since our aub file dumping's GTT handling is totally fake, we always put
everything in the low 4GB anyway and shouldn't ever need to set
AddressHigh to anything other than 0.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[ben: slight commit message change]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_bufmgr_gem.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 32a226c..3eb6e2e 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1944,12 +1944,14 @@ aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
 
 	aub_out(bufmgr_gem,
 		CMD_AUB_TRACE_HEADER_BLOCK |
-		(5 - 2));
+		((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
 	aub_out(bufmgr_gem,
 		AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
 	aub_out(bufmgr_gem, subtype);
 	aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
 	aub_out(bufmgr_gem, size);
+	if (bufmgr_gem->gen >= 8)
+		aub_out(bufmgr_gem, 0);
 	aub_write_bo_data(bo, offset, size);
 }
 
@@ -2034,12 +2036,14 @@ aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
 	 */
 	aub_out(bufmgr_gem,
 		CMD_AUB_TRACE_HEADER_BLOCK |
-		(5 - 2));
+		((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
 	aub_out(bufmgr_gem,
 		AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
 	aub_out(bufmgr_gem, 0); /* general/surface subtype */
 	aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
 	aub_out(bufmgr_gem, ring_count * 4);
+	if (bufmgr_gem->gen >= 8)
+		aub_out(bufmgr_gem, 0);
 
 	/* FIXME: Need some flush operations here? */
 	aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
@@ -2952,11 +2956,13 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
 	aub_out(bufmgr_gem, 0); /* comment len */
 
 	/* Set up the GTT. The max we can handle is 256M */
-	aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2));
+	aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
 	aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
 	aub_out(bufmgr_gem, 0); /* subtype */
 	aub_out(bufmgr_gem, 0); /* offset */
 	aub_out(bufmgr_gem, gtt_size); /* size */
+	if (bufmgr_gem->gen >= 8)
+		aub_out(bufmgr_gem, 0);
 	for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
 		aub_out(bufmgr_gem, entry);
 	}
-- 
1.8.4.2

[PATCH 5/5] intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps

[Ben Widawsky]

From: Damien Lespiau <damien.lespiau@intel.com>

The command now takes a 48bits address and is thus 1 byte longer.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 intel/intel_bufmgr_gem.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 3eb6e2e..029ca5d 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2028,8 +2028,14 @@ aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
 
 	/* Make a ring buffer to execute our batchbuffer. */
 	memset(ringbuffer, 0, sizeof(ringbuffer));
-	ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
-	ringbuffer[ring_count++] = batch_buffer;
+	if (bufmgr_gem->gen >= 8) {
+		ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
+		ringbuffer[ring_count++] = batch_buffer;
+		ringbuffer[ring_count++] = 0;
+	} else {
+		ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
+		ringbuffer[ring_count++] = batch_buffer;
+	}
 
 	/* Write out the ring.  This appears to trigger execution of
 	 * the ring in the simulator.
-- 
1.8.4.2

Re: [PATCH 5/5] intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps

[Eric Anholt]

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Ben Widawsky <benjamin.widawsky@intel.com> writes:

> From: Damien Lespiau <damien.lespiau@intel.com>
>
> The command now takes a 48bits address and is thus 1 byte longer.

I think you mean "1 dword"

Other than that, patches 2-5 are

Reviewed-by: Eric Anholt <eric@anholt.net>

(patch 1, I don't know anything about the set of PCI IDs so I've skipped
it).

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Re: [PATCH 0/5] BDW libdrm support

[Kenneth Graunke]

On 11/06/2013 09:15 AM, Ben Widawsky wrote:
> Nothing special here... I'm fine with not pushing any of the AUB stuff if
> anyone has issues.
> 
> Ben Widawsky (2):
>   intel/bdw: Add broadwell chipset IDs
>   intel/bdw: Handle gen8 bufmgr_init
> 
> Damien Lespiau (2):
>   intel/bdw: Add gen8 to the decode init
>   intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps
> 
> Kenneth Graunke (1):
>   intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.
> 
>  intel/intel_bufmgr_gem.c | 24 +++++++++++++++++++-----
>  intel/intel_chipset.h    | 22 +++++++++++++++++++++-
>  intel/intel_decode.c     |  4 +++-
>  3 files changed, 43 insertions(+), 7 deletions(-)

For the series:
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>