From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Richter Subject: Re: Workaround for flicker with panning on the i830 - found a way for tiled displays Date: Fri, 15 Nov 2013 17:08:45 +0100 Message-ID: <5286470D.3070004@math.tu-berlin.de> References: <1565_1384184620_5280FB2C_1565_9181_1_CAKMK7uF2UmKJHvVPrzE7-7A9DQ5JrLHAFnDiuVUDHFU+DoOXww@mail.gmail.com> <52825A28.3040500@math.tu-berlin.de> <1565_1384276909_528263AC_1565_19510_1_20131112172217.GB3741@phenom.ffwll.local> <5283D81A.1080105@math.tu-berlin.de> <26136_1384374018_5283DF02_26136_9623_1_20131113202049.GH7251@phenom.ffwll.local> <52847857.7070200@math.tu-berlin.de> <26136_1384417275_528487FB_26136_12808_1_CAKMK7uEfiAoFutfk=mtqteuV07t5SneGniyXnRet_T3Bs4spRw@mail.gmail.com> <52851358.6040801@math.tu-berlin.de> <26136_1384453961_52851749_26136_18549_1_20131114183308.GI22741@phenom.ffwll.local> <52861E9B.5080509@math.tu-berlin.de> <10422_1384530087_528640A7_10422_3841_1_20131115154159.GU22741@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from hydra.rus.uni-stuttgart.de (hydra.rus.uni-stuttgart.de [129.69.192.3]) by gabe.freedesktop.org (Postfix) with ESMTP id 70A1D1059B1 for ; Fri, 15 Nov 2013 08:08:54 -0800 (PST) In-Reply-To: <10422_1384530087_528640A7_10422_3841_1_20131115154159.GU22741@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org Am 15.11.2013 16:41, schrieb Daniel Vetter: > > Gosh, should have read the code more closely. We have a totally botched wm > setup on i830M - the watermark code for the 2nd pipe is just not there! (-: Guess that explains something. Just disregard my earlier patch, simply superfluous. In the meantime, I recompiled the code and *decreased* the latency from 5000 to 3000, then getting a stable image, even the boot console is then stable (has never been before). Its still off by half a screen, but no longer flickering left and right. However, what I do not understand about the watermark computation is that a *lower* latency results in a *higher* number of entries in the FIFO. Shouldn't this quite the reverse? In specific, I do not understand the subtraction in intel_calculate_wm, line 1058. Anyhow, I let you proceed with the patch and I'm ready and happy to test it. Greetings, Thomas