From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Richter Subject: Fwd: [PATCH] Watermark level workaround for i830 Date: Tue, 19 Nov 2013 10:55:37 +0100 Message-ID: <528B3599.4080202@math.tu-berlin.de> References: <5289E107.9090805@math.tu-berlin.de> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060502020001010206000606" Return-path: Received: from hydra.rus.uni-stuttgart.de (hydra.rus.uni-stuttgart.de [129.69.192.3]) by gabe.freedesktop.org (Postfix) with ESMTP id C7A6110D936 for ; Tue, 19 Nov 2013 02:19:58 -0800 (PST) In-Reply-To: <5289E107.9090805@math.tu-berlin.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --------------060502020001010206000606 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi Daniel, did you get this? (See below)? In the meantime, I also checked with video overlays, and the minimum value of 6 is not yet quite optimal, higher values (lower watermarks) seem to do even better. From the values I get, I also estimate a minimum latency of about 1100 ns, the default value of 5000 is much too high for the i830. There are two alternative possibilities to fix this: a) Include in the watermark structure not only a maximum value, but also a minimum value and modify calculate_wm accordingly, -and/or- c) include a latency value in the watermark structure, setting it to a lower value on i830. What do you think? Greetings, Thomas -------- Original-Nachricht -------- Betreff: [PATCH] Watermark level workaround for i830 Datum: Mon, 18 Nov 2013 10:42:31 +0100 Von: Thomas Richter An: Daniel Vetter Kopie (CC): intel-gfx@lists.freedesktop.org Hi Daniel, hi intel experts, please find a patch attached concerning the watermark levels on the i830 chipsets. I did a couple of experiments this morning and found that the watermark on i830 may neither be too small (i.e. the FW_BLC register values may not be too high) as otherwise the FIFO runs try, but for some strange reasons, the watermark may neither be too high (the FW_BLC register must not be too small) as otherwise the display flickers. Reasons for this are unclear at this moment, though the attached patch seems to remove flickering quite reliably on linear and tiled displays. What I should probably also report is that the watermark is set quite too low (i.e. much too conservative) on the R31. The computed values are 1 and 5 (for VGA and LVDS, respectively), though the minimum required levels are much higher, somewhere in the ballpark of 32. Greetings, Thomas --------------060502020001010206000606 Content-Type: text/x-patch; name="0003-Watermark-configuration-workaround-for-i830-chipsets.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0003-Watermark-configuration-workaround-for-i830-chipsets.pa"; filename*1="tch" >>From f535e532f3279e43a7f20bc96d4e62b24a9af684 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 18 Nov 2013 10:38:27 +0100 Subject: [PATCH 3/3] Watermark configuration workaround for i830 chipsets. For unclear reasons, the watermark level on i830 and related chipsets must not grow above 6 as otherwise display flickering will occurr, specifically on panning. Signed-off-by: Thomas Richter --- drivers/gpu/drm/i915/intel_pm.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 365545f..43c65f0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1648,6 +1648,21 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) I915_WRITE(FW_BLC_SELF, srwm & 0x3f); } + if (IS_I830(dev)) { + /* For unknown reasons, i830 chipsets run havok + * on panning if the watermark is below 6, + * thus adjust it accordingly. + */ + if (planea_wm < 6) { + planea_wm = 6; + DRM_DEBUG_KMS("i9xx plane A wm workaround enabled\n"); + } + if (planeb_wm < 6) { + planeb_wm = 6; + DRM_DEBUG_KMS("i9xx plane B wm workaround enabled\n"); + } + } + DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", planea_wm, planeb_wm, cwm, srwm); @@ -1692,6 +1707,16 @@ static void i830_update_wm(struct drm_crtc *unused_crtc) &i830_wm_info, dev_priv->display.get_fifo_size(dev, 0), 4, latency_ns); + + /* For unknown reasons, i830 chipsets run havok + * on panning if the watermark is below 6, + * thus adjust it accordingly. + */ + if (planea_wm < 6) { + planea_wm = 6; + DRM_DEBUG_KMS("i830 plane A wm workaround enabled\n"); + } + fwater_lo = I915_READ(FW_BLC) & ~0xfff; fwater_lo |= (3<<8) | planea_wm; -- 1.7.10.4 --------------060502020001010206000606 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --------------060502020001010206000606--