public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Vandana Kannan <vandana.kannan@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
Date: Wed, 18 Dec 2013 15:36:07 +0530	[thread overview]
Message-ID: <52B1738F.4030503@intel.com> (raw)
In-Reply-To: <20131218090155.GX22448@nuc-i3427.alporthouse.com>

On Dec-18-2013 2:31 PM, Chris Wilson wrote:
> On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote:
>> On Dec-17-2013 6:00 PM, Chris Wilson wrote:
>>> On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
>>>> For Broadwell, there is one instance of Transcoder MN values per transcoder.
>>>> For dynamic switching between multiple refreshr rates, M/N values may be
>>>> reprogrammed on the fly. Link N programming triggers update of all data and
>>>> link M & N registers and the new M/N values will be used in the next frame
>>>> that is output.
>>>>
>>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>>>> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/intel_dp.c |   23 +++++++++++++++++++----
>>>>  1 file changed, 19 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>>> index 209be3c..183cfd7 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>>> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>>>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>>>  	enum transcoder transcoder = crtc->config.cpu_transcoder;
>>>>  
>>>> -	if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
>>>> +	if (INTEL_INFO(dev)->gen >= 8) {
>>>> +		I915_WRITE(PIPE_DATA_M1(transcoder),
>>>> +			TU_SIZE(m_n->tu) | m_n->gmch_m);
>>>> +		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
>>>> +		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
>>>> +		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
>>>> +	} else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) {
>>>
>>> Ouch. Double ouch later.
>>> -Chris
>>>
>> We are looking to write in M1/N1 registers for BDW and M2/N2 registers
>> for HSW and below. What is your suggestion on how to implement this ?
> 
>   if (gen >= 8) {
>   } else if (gen >= 5) {
>   }
> 
> Or as you use gen >= 5 && gen < 8 elsewhere, a feature macro would be
> even more sensible, HAS_DRRS().
> -Chris
> 
I will make this change to
   if (gen >= 8) {
   } else if (gen >= 5) {
   }
- Vandana

  reply	other threads:[~2013-12-18 10:06 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-17  5:28 [PATCH 0/5] Enabling DRRS support in the kernel Vandana Kannan
2013-12-17  5:28 ` [PATCH 1/5] drm/i915: Adding VBT fields to support eDP DRRS feature Vandana Kannan
2013-12-17 12:26   ` Chris Wilson
2013-12-18  8:08     ` Vandana Kannan
2013-12-18  9:11       ` Chris Wilson
2013-12-18 10:13         ` Vandana Kannan
2013-12-17  5:28 ` [PATCH 2/5] drm/i915: Parse EDID probed modes for DRRS support Vandana Kannan
2013-12-17 12:28   ` Chris Wilson
2013-12-18  8:11     ` Vandana Kannan
2013-12-18  9:06       ` Chris Wilson
2013-12-18 10:12         ` Vandana Kannan
2013-12-19 11:51   ` Jani Nikula
2013-12-20  5:21     ` Vandana Kannan
2013-12-17  5:28 ` [PATCH 3/5] drm/i915: Add support for DRRS to switch RR Vandana Kannan
2013-12-17  5:28 ` [PATCH 4/5] drm/i915: Idleness detection for DRRS Vandana Kannan
2013-12-17 12:29   ` Chris Wilson
2013-12-18  8:18     ` Vandana Kannan
2013-12-18  9:04       ` Chris Wilson
2013-12-18 10:09         ` Vandana Kannan
2013-12-17  5:28 ` [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
2013-12-17 12:30   ` Chris Wilson
2013-12-18  8:24     ` Vandana Kannan
2013-12-18  9:01       ` Chris Wilson
2013-12-18 10:06         ` Vandana Kannan [this message]
2013-12-18  9:24 ` [PATCH 0/5] Enabling DRRS support in the kernel Daniel Vetter
2013-12-18 10:15   ` Vandana Kannan
  -- strict thread matches above, loose matches on Subject: below --
2013-12-19  8:30 [PATCH 0/5] Enabling DRRS " Vandana Kannan
2013-12-19  8:31 ` [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
2013-12-20 10:10 [PATCH 0/5] Enabling DRRS in the kernel Vandana Kannan
2013-12-20 10:10 ` [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
2013-12-23  7:52 [PATCH 0/5] Enabling DRRS in the kernel Vandana Kannan
2013-12-23  7:52 ` [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan
2014-01-22 14:34   ` Jani Nikula
2014-01-30  3:52     ` Vandana Kannan
2014-02-14 10:02 [PATCH 0/5] v5: Enabling DRRS in the kernel Vandana Kannan
2014-02-14 10:02 ` [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR Vandana Kannan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=52B1738F.4030503@intel.com \
    --to=vandana.kannan@intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox