From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kenneth Graunke Subject: Re: [PATCH 4/7] drm/i915: Disable SF pipelined attribute fetch for SNB Date: Fri, 07 Feb 2014 12:14:47 -0800 Message-ID: <52F53EB7.9020001@whitecape.org> References: <1391543961-1553-1-git-send-email-ville.syrjala@linux.intel.com> <1391543961-1553-5-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0110194241==" Return-path: Received: from homiemail-a61.g.dreamhost.com (caiajhbdcaib.dreamhost.com [208.97.132.81]) by gabe.freedesktop.org (Postfix) with ESMTP id 8756FFBCBD for ; Fri, 7 Feb 2014 12:11:43 -0800 (PST) In-Reply-To: <1391543961-1553-5-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --===============0110194241== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="a4s2c6PXsOnOWumo0rDnJPnFgqJqq5hXG" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --a4s2c6PXsOnOWumo0rDnJPnFgqJqq5hXG Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 02/04/2014 11:59 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=E4l=E4 >=20 > According to Bspec we need to disable SF pipelined attribute fetch > whenever SF outputs exceed 16 and normal clip mode is used. A quick > glance at Mesa suggests that these conditions could happen. So let's > just always set the magic bit. >=20 > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ > 2 files changed, 10 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > index 7aa2cf5..0334507 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -790,7 +790,8 @@ > #define _3D_CHICKEN3 0x02090 > #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) > #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) > -#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) > +#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */= > +#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6= */ > =20 > #define MI_MODE 0x0209c > # define VS_TIMER_DISPATCH (1 << 6) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > index 6a09281..7247084 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4683,6 +4683,14 @@ static void gen6_init_clock_gating(struct drm_de= vice *dev) > _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); > =20 > /* > + * Bspec says: > + * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal a= nd > + * 3DSTATE_SF number of SF output attributes is more than 16." > + */ > + I915_WRITE(_3D_CHICKEN3, > + _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH))= ; > + > + /* > * According to the spec the following bits should be > * set in order to enable memory self-refresh and fbc: > * The bit21 and bit22 of 0x42000 >=20 I'm almost positive Mesa will hit this case. Nice catch! Reviewed-by: Kenneth Graunke --a4s2c6PXsOnOWumo0rDnJPnFgqJqq5hXG Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAEBAgAGBQJS9T6+AAoJEFtb2gcdScw4EdsP/2IgTCeTQZMNK29o1zX1Qq2B H0k4y5erY/meH/BAOQBuuDMu3LE6gEjryASqp+fxGmOET/2Ud9oGnOij0CMBXEwU NBUSno8c4hATDFagznUz6xagSeAVq/r49TbM5/TyyLCM0J1Q5/bLVxlbn5kJ6DRs QEoJkkoC26Gb2XF6mh/89zGWNErn5gyKco0kg1fRXzBjUGBqXcSbGLEASVZ2V/gm bHU40pgGlEDu1ALlbSXaztA7TQi1NwbJGolXK56huFjBVIJzlEGggR3kPIeo73Ce CaTlxiNBPV3ZNtz+dH7G9tefNQNUChvG5GyWHswq2eA2YoqmGRKgI2FprjHo/oLT xwKRNGlRbQ/QwbpFZpskAxBn0+lvWCs/4rT/Mug0+34Go3BRJIFUGk6QMoOI6FNf Ngkyr8gpsCbFKnUa05/s3B8pdKH9ylx9poIxm9fxLppxbh8oaexgoDYR/P0mc1PF lzeJTC9C3cyADmfxnxk7R6WKqUssbgFy7R+vGVjCDn1ZTVlRfN8td65UhSAaDMqK 8P80MRVXYSPDu7pVS6WbIASf/qK/RcGb9vrEfBL/NXDhr3GpjDLfAQ4NCPeNlibn XbzGFlCldudyMMyJWAkqJ8pQM4wXEwrDNdgkPs2KMznP55Lf/bm+F9mlcRoSwCUB l7I7ii/IwpWK4tyDfDNZ =tvgM -----END PGP SIGNATURE----- --a4s2c6PXsOnOWumo0rDnJPnFgqJqq5hXG-- --===============0110194241== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0110194241==--