From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu Dai Subject: Re: [PATCH v4] drm/i915: add support for Z-order of planes for VLV. Date: Tue, 04 Mar 2014 17:37:39 -0800 Message-ID: <53167FE3.20800@intel.com> References: <1393884748-8508-1-git-send-email-yu.dai@intel.com> <20140304082021.GE17720@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0954081916==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 674AAFA374 for ; Tue, 4 Mar 2014 17:36:19 -0800 (PST) In-Reply-To: <20140304082021.GE17720@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0954081916== Content-Type: multipart/alternative; boundary="------------090509060404060601060702" This is a multi-part message in MIME format. --------------090509060404060601060702 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Chris, This looks like a hw specific value which is difficult to understand. However, the definition of these values are just a list of available options of z-order. On Intel VLV, there is only 6 options for the three planes Primary, Sprite A and Sprite B. Cursor is always on top. For example, "P1S1S2C1" means z-order (from bottom to top) of Primary -> Sprite A -> Sprite B -> Cursor. #define P1S1S2C1 0 #define P1S2S1C1 8 #define S2P1S1C1 1 #define S2S1P1C1 9 #define S1P1S2C1 4 #define S1S2P1C1 6 In theory, if hw supports, each CRTC may have their own plane z-order if user intentionally wants that happens. The pipe info (0 or 1) is packed into z-order value with extra bit (bit 31). Thanks, Alex On 14-03-04 12:20 AM, Chris Wilson wrote: > On Mon, Mar 03, 2014 at 02:12:28PM -0800, yu.dai@intel.com wrote: >> From: "Yu(Alex) Dai" >> >> Add "zorder" property to crtc to control Z-order of sprite and >> primary planes. The alpha channel of the planes can be enabled or >> disabled during Z-order change. > > Can I just say that is an abonimal user interface. You expect the > client to encode a hw specific value into a CRTC property that > affects global state. and given the two properties on the two CRTCs, > which should userspace believe? -Chris > --------------090509060404060601060702 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Chris,

This looks like a hw specific value which is difficult to understand. However, the definition of these values are just a list of available options of z-order. On Intel VLV, there is only 6 options for the three planes Primary, Sprite A and Sprite B. Cursor is always on top. For example, "P1S1S2C1" means z-order (from bottom to top) of Primary -> Sprite A -> Sprite B -> Cursor.

#define P1S1S2C1        0
#define P1S2S1C1        8
#define S2P1S1C1        1
#define S2S1P1C1        9
#define S1P1S2C1        4
#define S1S2P1C1        6

In theory, if hw supports, each CRTC may have their own plane z-order if user intentionally wants that happens. The pipe info (0 or 1) is packed into z-order value with extra bit (bit 31).

Thanks,
Alex

On 14-03-04 12:20 AM, Chris Wilson wrote:
> On Mon, Mar 03, 2014 at 02:12:28PM -0800, yu.dai@intel.com wrote:
>> From: "Yu(Alex) Dai" <yu.dai@intel.com>
>>
>> Add "zorder" property to crtc to control Z-order of sprite and
>> primary planes. The alpha channel of the planes can be enabled or
>> disabled during Z-order change.
>
> Can I just say that is an abonimal user interface. You expect the
> client to encode a hw specific value into a CRTC property that
> affects global state. and given the two properties on the two CRTCs,
> which should userspace believe? -Chris
>


--------------090509060404060601060702-- --===============0954081916== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0954081916==--