From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak S Subject: Re: [PATCH 3/3] drm/i915: Mask PM interrupt generation when at up/down limits Date: Thu, 27 Mar 2014 20:21:29 +0530 Message-ID: <53343AF1.20906@linux.intel.com> References: <1395908661-7355-1-git-send-email-chris@chris-wilson.co.uk> <1395908661-7355-3-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1396812330==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C5C226E72D for ; Thu, 27 Mar 2014 07:51:59 -0700 (PDT) In-Reply-To: <1395908661-7355-3-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Deepak S List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============1396812330== Content-Type: multipart/alternative; boundary="------------090808090509020203000908" This is a multi-part message in MIME format. --------------090808090509020203000908 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote: > The speculation is that we can conserve more power by masking off the > interrupts at source (PMINTRMSK) rather than filtering them by the > up/down thresholds (RPINTLIM). > > Signed-off-by: Chris Wilson > Cc: Deepak S > Cc: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++------------ > 1 file changed, 20 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > index 3ad590924062..0a76e9baeca2 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3006,6 +3006,25 @@ static void gen6_set_rps_thresholds(struct drm_i= 915_private *dev_priv, u8 val) > dev_priv->rps.last_adj =3D 0; > } > =20 > +static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) > +{ > + u32 mask; > + > + mask =3D GEN6_PM_RP_DOWN_TIMEOUT; > + if (val > dev_priv->rps.min_freq_softlimit) > + mask |=3D GEN6_PM_RP_DOWN_THRESHOLD; > + if (val < dev_priv->rps.max_freq_softlimit) > + mask |=3D GEN6_PM_RP_UP_THRESHOLD; > + > + /* IVB and SNB hard hangs on looping batchbuffer > + * if GEN6_PM_UP_EI_EXPIRED is masked. > + */ > + if (INTEL_INFO(dev_priv->dev)->gen <=3D 7 && !IS_HASWELL(dev_priv->de= v)) > + mask |=3D GEN6_PM_RP_UP_EI_EXPIRED; > + > + return ~mask; > +} > + > /* gen6_set_rps is called to update the frequency request, but should= also be > * called when the range (min_delay and max_delay) is modified so tha= t we can > * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ > @@ -3037,6 +3056,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val) > * until we hit the minimum or maximum frequencies. > */ > I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val))= ; > + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); > =20 > POSTING_READ(GEN6_RPNSWREQ); > =20 > @@ -3220,24 +3240,12 @@ int intel_enable_rc6(const struct drm_device *d= ev) > static void gen6_enable_rps_interrupts(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > - u32 enabled_intrs; > =20 > spin_lock_irq(&dev_priv->irq_lock); > WARN_ON(dev_priv->rps.pm_iir); > snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); > spin_unlock_irq(&dev_priv->irq_lock); > - > - /* only unmask PM interrupts we need. Mask all others. */ > - enabled_intrs =3D dev_priv->pm_rps_events; > - > - /* IVB and SNB hard hangs on looping batchbuffer > - * if GEN6_PM_UP_EI_EXPIRED is masked. > - */ > - if (INTEL_INFO(dev)->gen <=3D 7 && !IS_HASWELL(dev)) > - enabled_intrs |=3D GEN6_PM_RP_UP_EI_EXPIRED; > - > - I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs); > } > =20 > static void gen8_enable_rps(struct drm_device *dev) On VLV, gen6_enable_rps_interrupts is used to enable turbo=20 interrutpts. I think we need to extend gen6_rps_pm_maskto valleyview also= ? --------------090808090509020203000908 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
The speculation is that we can conserve more power b=
y masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Deepak S <deepak.s@intel.com>
Cc: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.intel.com>=

---
 drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++------------
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel=
_pm.c
index 3ad590924062..0a76e9baeca2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3006,6 +3006,25 @@ static void gen6_set_rps_thresholds(struct drm_i91=
5_private *dev_priv, u8 val)
 	dev_priv->rps.last_adj =3D 0;
 }
=20
+static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+{
+	u32 mask;
+
+	mask =3D GEN6_PM_RP_DOWN_TIMEOUT;
+	if (val > dev_priv->rps.min_freq_softlimit)
+		mask |=3D GEN6_PM_RP_DOWN_THRESHOLD;
+	if (val < dev_priv->rps.max_freq_softlimit)
+		mask |=3D GEN6_PM_RP_UP_THRESHOLD;
+
+	/* IVB and SNB hard hangs on looping batchbuffer
+	 * if GEN6_PM_UP_EI_EXPIRED is masked.
+	 */
+	if (INTEL_INFO(dev_priv->dev)->gen <=3D 7 && !IS_HASWE=
LL(dev_priv->dev))
+		mask |=3D GEN6_PM_RP_UP_EI_EXPIRED;
+
+	return ~mask;
+}
+
 /* gen6_set_rps is called to update the frequency request, but should al=
so be
  * called when the range (min_delay and max_delay) is modified so that w=
e can
  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
@@ -3037,6 +3056,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	 * until we hit the minimum or maximum frequencies.
 	 */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
=20
 	POSTING_READ(GEN6_RPNSWREQ);
=20
@@ -3220,24 +3240,12 @@ int intel_enable_rc6(const struct drm_device *dev=
)
 static void gen6_enable_rps_interrupts(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv =3D dev->dev_private;
-	u32 enabled_intrs;
=20
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON(dev_priv->rps.pm_iir);
 	snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 	I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
 	spin_unlock_irq(&dev_priv->irq_lock);
-
-	/* only unmask PM interrupts we need. Mask all others. */
-	enabled_intrs =3D dev_priv->pm_rps_events;
-
-	/* IVB and SNB hard hangs on looping batchbuffer
-	 * if GEN6_PM_UP_EI_EXPIRED is masked.
-	 */
-	if (INTEL_INFO(dev)->gen <=3D 7 && !IS_HASWELL(dev))
-		enabled_intrs |=3D GEN6_PM_RP_UP_EI_EXPIRED;
-
-	I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
 }
=20
 static void gen8_enable_rps(struct drm_device *dev)
On VLV,=C2=A0 gen6_enable_rps_interrupts=C2=A0 is used to enab= le turbo interrutpts. I think we need to extend gen6_rps_pm_mask=C2=A0 to valleyview also?
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