From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak S Subject: Re: [PATCH] drm/i915: Mask PM/RPS interrupt generation based on activity Date: Sun, 30 Mar 2014 12:08:35 +0530 Message-ID: <5337BBEB.6080305@linux.intel.com> References: <53343AF1.20906@linux.intel.com> <1395993814-11337-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 139916E021 for ; Sat, 29 Mar 2014 23:38:38 -0700 (PDT) In-Reply-To: <1395993814-11337-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Friday 28 March 2014 01:33 PM, Chris Wilson wrote: > The speculation is that we can conserve more power by masking off > the interrupts at source (PMINTRMSK) rather than filtering them by the > up/down thresholds (RPINTLIM). We can select which events we know will > be active based on the current frequency versus our imposed range, i.e. > if at minimum, we know we will not want to generate any more > down-interrupts and vice versa. > > v2: We only need the TIMEOUT when above min frequency. > v3: Tweak VLV at the same time > > Signed-off-by: Chris Wilson > Cc: Deepak S > --- > I see your point that I cannot remove PMINTRMSK from enable_interrupts > without tweaking VLV at the same time. I did consider making this 4 > patches (factor out gen6_rps_pm_mask, tweak gen6+, tweak, vlv, remove it > from enable_interrupts) but decided that was just being silly and > squashed the two patches together instead. > --- > drivers/gpu/drm/i915/intel_pm.c | 41 +++++++++++++++++++++++++---------------- > 1 file changed, 25 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 154aa07d51a7..35a7b5b65883 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3006,6 +3006,24 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > dev_priv->rps.last_adj = 0; > } > > +static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) > +{ > + u32 mask = 0; > + > + if (val > dev_priv->rps.min_freq_softlimit) > + mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; > + if (val < dev_priv->rps.max_freq_softlimit) > + mask |= GEN6_PM_RP_UP_THRESHOLD; > + > + /* IVB and SNB hard hangs on looping batchbuffer > + * if GEN6_PM_UP_EI_EXPIRED is masked. > + */ > + if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) > + mask |= GEN6_PM_RP_UP_EI_EXPIRED; > + > + return ~mask; > +} > + > /* gen6_set_rps is called to update the frequency request, but should also be > * called when the range (min_delay and max_delay) is modified so that we can > * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ > @@ -3037,6 +3055,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val) > * until we hit the minimum or maximum frequencies. > */ > I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); > + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); > > POSTING_READ(GEN6_RPNSWREQ); > > @@ -3089,6 +3108,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) > I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, > I915_READ(VLV_GTLC_SURVIVABILITY_REG) & > ~VLV_GFX_CLK_FORCE_ON_BIT); > + > + I915_WRITE(GEN6_PMINTRMSK, > + gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); > } > > void gen6_rps_idle(struct drm_i915_private *dev_priv) > @@ -3134,13 +3156,12 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) > dev_priv->rps.cur_freq, > vlv_gpu_freq(dev_priv, val), val); > > - if (val == dev_priv->rps.cur_freq) > - return; > + if (val != dev_priv->rps.cur_freq) > + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); > > - vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); > + I915_WRITE(GEN6_PMINTRMSK, val); > > dev_priv->rps.cur_freq = val; > - > trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); > } > > @@ -3220,24 +3241,12 @@ int intel_enable_rc6(const struct drm_device *dev) > static void gen6_enable_rps_interrupts(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - u32 enabled_intrs; > > spin_lock_irq(&dev_priv->irq_lock); > WARN_ON(dev_priv->rps.pm_iir); > snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); > I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); > spin_unlock_irq(&dev_priv->irq_lock); > - > - /* only unmask PM interrupts we need. Mask all others. */ > - enabled_intrs = dev_priv->pm_rps_events; > - > - /* IVB and SNB hard hangs on looping batchbuffer > - * if GEN6_PM_UP_EI_EXPIRED is masked. > - */ > - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) > - enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED; > - > - I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs); > } > > static void gen8_enable_rps(struct drm_device *dev) Reviewed-by:Deepak S