From: Deepak S <deepak.s@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Refactor gen6_set_rps
Date: Sun, 30 Mar 2014 12:15:01 +0530 [thread overview]
Message-ID: <5337BD6D.7010500@linux.intel.com> (raw)
In-Reply-To: <1395908661-7355-2-git-send-email-chris@chris-wilson.co.uk>
On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
> What used to be a short-circuit now needs to adjust interrupt masking in
> response to user requests for changing the min/max allowed frequencies.
> This is currently done by a special case and early return, but the next
> patch adds another common action to take, so refactor the code to reduce
> duplication.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++--------------------
> 1 file changed, 14 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index edf1b29d9856..3ad590924062 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3017,36 +3017,30 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
> WARN_ON(val > dev_priv->rps.max_freq_softlimit);
> WARN_ON(val < dev_priv->rps.min_freq_softlimit);
>
> - if (val == dev_priv->rps.cur_freq) {
> - /* min/max delay may still have been modified so be sure to
> - * write the limits value */
> - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> - gen6_rps_limits(dev_priv, val));
> + /* min/max delay may still have been modified so be sure to
> + * write the limits value.
> + */
> + if (val != dev_priv->rps.cur_freq) {
> + gen6_set_rps_thresholds(dev_priv, val);
>
> - return;
> + if (IS_HASWELL(dev))
> + I915_WRITE(GEN6_RPNSWREQ,
> + HSW_FREQUENCY(val));
> + else
> + I915_WRITE(GEN6_RPNSWREQ,
> + GEN6_FREQUENCY(val) |
> + GEN6_OFFSET(0) |
> + GEN6_AGGRESSIVE_TURBO);
> }
>
> - gen6_set_rps_thresholds(dev_priv, val);
> -
> - if (IS_HASWELL(dev))
> - I915_WRITE(GEN6_RPNSWREQ,
> - HSW_FREQUENCY(val));
> - else
> - I915_WRITE(GEN6_RPNSWREQ,
> - GEN6_FREQUENCY(val) |
> - GEN6_OFFSET(0) |
> - GEN6_AGGRESSIVE_TURBO);
> -
> /* Make sure we continue to get interrupts
> * until we hit the minimum or maximum frequencies.
> */
> - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> - gen6_rps_limits(dev_priv, val));
> + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
>
> POSTING_READ(GEN6_RPNSWREQ);
>
> dev_priv->rps.cur_freq = val;
> -
> trace_intel_gpu_freq_change(val * 50);
> }
>
Reviewed-by:Deepak S <deepak.s@linux.intel.com>
next prev parent reply other threads:[~2014-03-30 6:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-27 8:24 [PATCH 1/3] Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq." Chris Wilson
2014-03-27 8:24 ` [PATCH 2/3] drm/i915: Refactor gen6_set_rps Chris Wilson
2014-03-30 6:45 ` Deepak S [this message]
2014-03-27 8:24 ` [PATCH 3/3] drm/i915: Mask PM interrupt generation when at up/down limits Chris Wilson
2014-03-27 8:34 ` Chris Wilson
2014-03-27 8:35 ` [PATCH] drm/i915: Mask PM interrupt generation when at up/down limits for VLV Chris Wilson
2014-03-27 8:46 ` Chris Wilson
2014-03-27 14:51 ` [PATCH 3/3] drm/i915: Mask PM interrupt generation when at up/down limits Deepak S
2014-03-27 15:26 ` Chris Wilson
2014-03-28 8:03 ` [PATCH] drm/i915: Mask PM/RPS interrupt generation based on activity Chris Wilson
2014-03-30 6:38 ` Deepak S
2014-03-31 8:30 ` Daniel Vetter
2014-03-30 6:48 ` [PATCH 1/3] Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq." Deepak S
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