[PATCH 0/7] Updated MIPI sequence for BYT

[PATCH 0/7] Updated MIPI sequence for BYT

[Shobhit Kumar]

Hi,
The changes in DSI sequence are as suggested by HW and SV teams. Notable
difference apart form few WAs is that for MIPI it is suggetsed that the
PORT is enabled before PIPE and PLANE. The patch makes these changes.
So few sequence changes, few workarounds and few new feature support like
Clockstop.

A generic panel driver to enable MIPI is planned in next patchset

Known issue - 
Today the upstream kernel does not have PMIC driver amd these patches works if 
UEFI BIOS enables MIPI and reuse  BKL_EN, PANEL_EN from there, but during
suspend/resume things will still fail.

Regards
Shobhit

Shobhit Kumar (7):
  drm/i915: Program Rcomp and band gap reset everytime we resume from power gate
  drm/i915: Enable MIPI port before the plane and pipe enable
  drm/i915: Disable DPOunit clock gating
  drm/i915: Parameterize the Clockstop and escape_clk_div
  drm/i915: Panel commands can be sent only when clock is in LP11
  drm/i915: Send DPI command explicitely in LP mode
  drm/i915: Enable RANDOM resolution support for MIPI panels

 drivers/gpu/drm/i915/intel_dsi.c     | 125 +++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dsi.h     |   4 +-
 drivers/gpu/drm/i915/intel_dsi_cmd.c |   4 +-
 drivers/gpu/drm/i915/intel_dsi_cmd.h |   5 +-
 4 files changed, 108 insertions(+), 30 deletions(-)

-- 
1.8.3.2

[PATCH 1/7] drm/i915: Program Rcomp and band gap reset everytime we resume from power gate

[Shobhit Kumar]

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3365664..7ceb8c6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -110,6 +110,15 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
 	DRM_DEBUG_KMS("\n");
 
+	mutex_lock(&dev_priv->dpio_lock);
+	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
+	 * needed everytime after power gate */
+	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	/* bandgap reset is needed after everytime we do power gate */
+	band_gap_reset(dev_priv);
+
 	val = I915_READ(MIPI_PORT_CTRL(pipe));
 	I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 	usleep_range(1000, 1500);
@@ -379,9 +388,6 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 
-	/* XXX: Location of the call */
-	band_gap_reset(dev_priv);
-
 	/* escape clock divider, 20MHz, shared for A and C. device ready must be
 	 * off when doing this! txclkesc? */
 	tmp = I915_READ(MIPI_CTRL(0));
-- 
1.8.3.2

[PATCH 2/7] drm/i915: Enable MIPI port before the plane and pipe enable

[Shobhit Kumar]

As per the hw team's recommendation we need to enable the MIPI port
before enabling the plane and pipe. So call MIPI port enable in
pre_enable phase itself

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 51 ++++++++++++++++++++++++++--------------
 1 file changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 7ceb8c6..569e6c6 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -131,21 +131,6 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 	I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 	usleep_range(2000, 2500);
 }
-static void intel_dsi_pre_enable(struct intel_encoder *encoder)
-{
-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-
-	DRM_DEBUG_KMS("\n");
-
-	if (intel_dsi->dev.dev_ops->panel_reset)
-		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
-
-	/* put device in ready state */
-	intel_dsi_device_ready(encoder);
-
-	if (intel_dsi->dev.dev_ops->send_otp_cmds)
-		intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
-}
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
 {
@@ -165,15 +150,45 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 		dpi_send_cmd(intel_dsi, TURN_ON);
 		msleep(100);
 
+		if (intel_dsi->dev.dev_ops->enable)
+			intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
+
 		/* assert ip_tg_enable signal */
 		temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 		temp = temp | intel_dsi->port_bits;
 		I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 		POSTING_READ(MIPI_PORT_CTRL(pipe));
 	}
+}
+
+static void intel_dsi_pre_enable(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+	DRM_DEBUG_KMS("\n");
+
+	if (intel_dsi->dev.dev_ops->panel_reset)
+		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
+
+	/* put device in ready state */
+	intel_dsi_device_ready(encoder);
 
-	if (intel_dsi->dev.dev_ops->enable)
-		intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
+	if (intel_dsi->dev.dev_ops->send_otp_cmds)
+		intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
+
+	/* Enable port in pre-enable phase itself because as per hw team
+	 * recommendation, port should be enabled befor plane & pipe */
+	intel_dsi_enable(encoder);
+}
+
+static void intel_dsi_enable_nop(struct intel_encoder *encoder)
+{
+	DRM_DEBUG_KMS("\n");
+
+	/* for DSI port enable has to be done before pipe
+	 * and plane enable, so port enable is done in
+	 * pre_enable phase itself unlike other encoders
+	 */
 }
 
 static void intel_dsi_disable(struct intel_encoder *encoder)
@@ -600,7 +615,7 @@ bool intel_dsi_init(struct drm_device *dev)
 	intel_encoder->compute_config = intel_dsi_compute_config;
 	intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 	intel_encoder->pre_enable = intel_dsi_pre_enable;
-	intel_encoder->enable = intel_dsi_enable;
+	intel_encoder->enable = intel_dsi_enable_nop;
 	intel_encoder->mode_set = intel_dsi_mode_set;
 	intel_encoder->disable = intel_dsi_disable;
 	intel_encoder->post_disable = intel_dsi_post_disable;
-- 
1.8.3.2

[PATCH 3/7] drm/i915: Disable DPOunit clock gating

[Shobhit Kumar]

Otherwise, this can stall pipe. We also need DPLL REFA always
enabled

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 569e6c6..4793a5b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -163,16 +163,31 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 {
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	u32 tmp;
 
 	DRM_DEBUG_KMS("\n");
 
-	if (intel_dsi->dev.dev_ops->panel_reset)
-		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
+	/* Disable DPOunit clock gating, can stall pipe
+	 * and we need DPLL REFA always enabled */
+	tmp = I915_READ(DPLL(pipe));
+	tmp |= DPLL_REFA_CLK_ENABLE_VLV;
+	I915_WRITE(DPLL(pipe), tmp);
+
+	tmp = I915_READ(DSPCLK_GATE_D);
+	tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
+	I915_WRITE(DSPCLK_GATE_D, tmp);
 
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
 
+	if (intel_dsi->dev.dev_ops->panel_reset)
+		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
+
 	if (intel_dsi->dev.dev_ops->send_otp_cmds)
 		intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 
@@ -251,14 +266,21 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 
 	vlv_disable_dsi_pll(encoder);
 }
+
 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 {
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 val;
 
 	DRM_DEBUG_KMS("\n");
 
 	intel_dsi_clear_device_ready(encoder);
 
+	val = I915_READ(DSPCLK_GATE_D);
+	val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
+	I915_WRITE(DSPCLK_GATE_D, val);
+
 	if (intel_dsi->dev.dev_ops->disable_panel_power)
 		intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 }
-- 
1.8.3.2

[PATCH 4/7] drm/i915: Parameterize the Clockstop and escape_clk_div

[Shobhit Kumar]

In preparation for Generic driver

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++++--
 drivers/gpu/drm/i915/intel_dsi.h |  4 +++-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4793a5b..dfcdb10 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -495,10 +495,17 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 	/* dphy stuff */
 
 	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
+	I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
+
+	val = 0;
+	if (intel_dsi->eotp_pkt == 0)
+		val |= EOT_DISABLE;
+
+	if (intel_dsi->clock_stop)
+		val |= CLOCKSTOP;
 
 	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
+	I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 
 	/* in terms of txbyteclkhs. actual high to low switch +
 	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index b4a27ce..550714c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -95,8 +95,10 @@ struct intel_dsi {
 	u32 video_mode_format;
 
 	/* eot for MIPI_EOT_DISABLE register */
-	u32 eot_disable;
+	u8 eotp_pkt;
+	u8 clock_stop;
 
+	u8 escape_clk_div;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
-- 
1.8.3.2

[PATCH 5/7] drm/i915: Panel commands can be sent only when clock is in LP11

[Shobhit Kumar]

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index dfcdb10..d8eccda 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -229,6 +229,23 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		msleep(2);
 	}
 
+	/* Panel commands can be sent when clock is in LP11 */
+	I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
+
+	temp = I915_READ(MIPI_CTRL(pipe));
+	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+	I915_WRITE(MIPI_CTRL(pipe), temp |
+			intel_dsi->escape_clk_div <<
+			ESCAPE_CLOCK_DIVIDER_SHIFT);
+
+	I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
+
+	temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
+	temp &= ~VID_MODE_FORMAT_MASK;
+	I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
+
+	I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
+
 	/* if disable packets are sent before sending shutdown packet then in
 	 * some next enable sequence send turn on packet error is observed */
 	if (intel_dsi->dev.dev_ops->disable)
-- 
1.8.3.2

[PATCH 6/7] drm/i915: Send DPI command explicitely in LP mode

[Shobhit Kumar]

Though HS mode also should work.

v2: Change parameter as "bool hs" as suggested by Jani

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     | 5 +++--
 drivers/gpu/drm/i915/intel_dsi_cmd.c | 4 ++--
 drivers/gpu/drm/i915/intel_dsi_cmd.h | 5 ++++-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d8eccda..b5948b7 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -147,7 +147,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 		I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 	else {
 		msleep(20); /* XXX */
-		dpi_send_cmd(intel_dsi, TURN_ON);
+		dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 		msleep(100);
 
 		if (intel_dsi->dev.dev_ops->enable)
@@ -218,7 +218,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("\n");
 
 	if (is_vid_mode(intel_dsi)) {
-		dpi_send_cmd(intel_dsi, SHUTDOWN);
+		/* Send Shutdown command to the panel in LP mode */
+		dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 		msleep(10);
 
 		/* de-assert ip_tg_enable signal */
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 7c40f98..3eeb21b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -389,7 +389,7 @@ int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
  *
  * XXX: commands with data in MIPI_DPI_DATA?
  */
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
 	struct drm_device *dev = encoder->dev;
@@ -399,7 +399,7 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
 	u32 mask;
 
 	/* XXX: pipe, hs */
-	if (intel_dsi->hs)
+	if (hs)
 		cmd &= ~DPI_LP_MODE;
 	else
 		cmd |= DPI_LP_MODE;
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 54c8a23..9a18cbf 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -33,6 +33,9 @@
 #include "intel_drv.h"
 #include "intel_dsi.h"
 
+#define DPI_LP_MODE_EN	false
+#define DPI_HS_MODE_EN	true
+
 void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
 
 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
@@ -47,7 +50,7 @@ int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 			u8 *reqdata, int reqlen, u8 *buf, int buflen);
 
-int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd);
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
 
 /* XXX: questionable write helpers */
 static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
-- 
1.8.3.2

[PATCH 7/7] drm/i915: Enable RANDOM resolution support for MIPI panels

[Shobhit Kumar]

Some MIPI panels might not have resolution which is a multiple of 64 like
1366x768. Enable this feature for such panels by default

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b5948b7..4e271c7 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -552,9 +552,14 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 		   intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 
 	if (is_vid_mode(intel_dsi))
+		/* Some panels might have resolution which is not a multiple of
+		 * 64 like 1366 x 768. Enable RANDOM resolution support for such
+		 * panels by default */
 		I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 				intel_dsi->video_frmt_cfg_bits |
-				intel_dsi->video_mode_format);
+				intel_dsi->video_mode_format |
+				IP_TG_CONFIG |
+				RANDOM_DPI_DISPLAY_RESOLUTION);
 }
 
 static enum drm_connector_status
-- 
1.8.3.2

Re: [PATCH 0/7] Updated MIPI sequence for BYT

[Daniel Vetter]

On Wed, Apr 09, 2014 at 01:59:29PM +0530, Shobhit Kumar wrote:
> Hi,
> The changes in DSI sequence are as suggested by HW and SV teams. Notable
> difference apart form few WAs is that for MIPI it is suggetsed that the
> PORT is enabled before PIPE and PLANE. The patch makes these changes.
> So few sequence changes, few workarounds and few new feature support like
> Clockstop.
> 
> A generic panel driver to enable MIPI is planned in next patchset
> 
> Known issue - 
> Today the upstream kernel does not have PMIC driver amd these patches works if 
> UEFI BIOS enables MIPI and reuse  BKL_EN, PANEL_EN from there, but during
> suspend/resume things will still fail.

Thanks a lot for the patches&review, looking forward to the next round.
Hopefully that one will fix our mipi/dsi code to Just Work (tm) so that we
can close the asus 100t bug on kernel.org:

https://bugzilla.kernel.org/show_bug.cgi?id=68451

Cheers, Daniel
> 
> Regards
> Shobhit
> 
> Shobhit Kumar (7):
>   drm/i915: Program Rcomp and band gap reset everytime we resume from power gate
>   drm/i915: Enable MIPI port before the plane and pipe enable
>   drm/i915: Disable DPOunit clock gating
>   drm/i915: Parameterize the Clockstop and escape_clk_div
>   drm/i915: Panel commands can be sent only when clock is in LP11
>   drm/i915: Send DPI command explicitely in LP mode
>   drm/i915: Enable RANDOM resolution support for MIPI panels
> 
>  drivers/gpu/drm/i915/intel_dsi.c     | 125 +++++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_dsi.h     |   4 +-
>  drivers/gpu/drm/i915/intel_dsi_cmd.c |   4 +-
>  drivers/gpu/drm/i915/intel_dsi_cmd.h |   5 +-
>  4 files changed, 108 insertions(+), 30 deletions(-)
> 
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/7] Updated MIPI sequence for BYT

[Kumar, Shobhit]

On 4/9/2014 8:21 PM, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 01:59:29PM +0530, Shobhit Kumar wrote:
>> Hi,
>> The changes in DSI sequence are as suggested by HW and SV teams. Notable
>> difference apart form few WAs is that for MIPI it is suggetsed that the
>> PORT is enabled before PIPE and PLANE. The patch makes these changes.
>> So few sequence changes, few workarounds and few new feature support like
>> Clockstop.
>>
>> A generic panel driver to enable MIPI is planned in next patchset
>>
>> Known issue -
>> Today the upstream kernel does not have PMIC driver amd these patches works if
>> UEFI BIOS enables MIPI and reuse  BKL_EN, PANEL_EN from there, but during
>> suspend/resume things will still fail.
>
> Thanks a lot for the patches&review, looking forward to the next round.
> Hopefully that one will fix our mipi/dsi code to Just Work (tm) so that we
> can close the asus 100t bug on kernel.org:
>
> https://bugzilla.kernel.org/show_bug.cgi?id=68451

Thanks Daniel. Now the panel driver in next patch will definitely get 
the asus 100t booting at-least as I have got the patches already 
verified by those who have the device.

Regards
Shobhit

Re: [PATCH 0/7] Updated MIPI sequence for BYT

[Daniel Vetter]

On Wed, Apr 09, 2014 at 09:31:29PM +0530, Kumar, Shobhit wrote:
> On 4/9/2014 8:21 PM, Daniel Vetter wrote:
> >On Wed, Apr 09, 2014 at 01:59:29PM +0530, Shobhit Kumar wrote:
> >>Hi,
> >>The changes in DSI sequence are as suggested by HW and SV teams. Notable
> >>difference apart form few WAs is that for MIPI it is suggetsed that the
> >>PORT is enabled before PIPE and PLANE. The patch makes these changes.
> >>So few sequence changes, few workarounds and few new feature support like
> >>Clockstop.
> >>
> >>A generic panel driver to enable MIPI is planned in next patchset
> >>
> >>Known issue -
> >>Today the upstream kernel does not have PMIC driver amd these patches works if
> >>UEFI BIOS enables MIPI and reuse  BKL_EN, PANEL_EN from there, but during
> >>suspend/resume things will still fail.
> >
> >Thanks a lot for the patches&review, looking forward to the next round.
> >Hopefully that one will fix our mipi/dsi code to Just Work (tm) so that we
> >can close the asus 100t bug on kernel.org:
> >
> >https://bugzilla.kernel.org/show_bug.cgi?id=68451
> 
> Thanks Daniel. Now the panel driver in next patch will definitely
> get the asus 100t booting at-least as I have got the patches already
> verified by those who have the device.

Awesome, that should make a lot of people happy!

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch