* [PATCH] drm/i915: Add more registers to the whitelist for mesa
@ 2014-04-08 21:18 bradley.d.volkin
2014-04-09 13:34 ` Daniel Vetter
2014-04-09 16:22 ` Kenneth Graunke
0 siblings, 2 replies; 6+ messages in thread
From: bradley.d.volkin @ 2014-04-08 21:18 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
These are additional registers needed for performance monitoring and
ARB_draw_indirect extensions in mesa.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 29184d6..3486ef7 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -408,10 +408,19 @@ static const u32 gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
OACONTROL, /* Only allowed for LRI and SRM. See below. */
+ GEN7_3DPRIM_START_VERTEX,
+ GEN7_3DPRIM_VERTEX_COUNT,
+ GEN7_3DPRIM_INSTANCE_COUNT,
+ GEN7_3DPRIM_START_INSTANCE,
+ GEN7_3DPRIM_BASE_VERTEX,
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
+ REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
+ REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
+ REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
+ REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
GEN7_SO_WRITE_OFFSET(0),
GEN7_SO_WRITE_OFFSET(1),
GEN7_SO_WRITE_OFFSET(2),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e60737..533ec0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -427,6 +427,14 @@
/* There are the 4 64-bit counter registers, one for each stream output */
#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
+#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
+
+#define GEN7_3DPRIM_START_VERTEX 0x2430
+#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
+#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
+#define GEN7_3DPRIM_START_INSTANCE 0x243C
+#define GEN7_3DPRIM_BASE_VERTEX 0x2440
+
#define OACONTROL 0x2360
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Add more registers to the whitelist for mesa
2014-04-08 21:18 [PATCH] drm/i915: Add more registers to the whitelist for mesa bradley.d.volkin
@ 2014-04-09 13:34 ` Daniel Vetter
2014-04-09 16:22 ` Kenneth Graunke
1 sibling, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-04-09 13:34 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Tue, Apr 08, 2014 at 02:18:58PM -0700, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> These are additional registers needed for performance monitoring and
> ARB_draw_indirect extensions in mesa.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Queued for -next, thanks for the patch. Ken, can you pls take a look to
make sure that this is indeed what mesa wants? I've read around in the
mesa code and Brad's patch looks sane, but I definitely lack experience in
this area.
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +++++++++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 29184d6..3486ef7 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -408,10 +408,19 @@ static const u32 gen7_render_regs[] = {
> REG64(PS_INVOCATION_COUNT),
> REG64(PS_DEPTH_COUNT),
> OACONTROL, /* Only allowed for LRI and SRM. See below. */
> + GEN7_3DPRIM_START_VERTEX,
> + GEN7_3DPRIM_VERTEX_COUNT,
> + GEN7_3DPRIM_INSTANCE_COUNT,
> + GEN7_3DPRIM_START_INSTANCE,
> + GEN7_3DPRIM_BASE_VERTEX,
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
> GEN7_SO_WRITE_OFFSET(0),
> GEN7_SO_WRITE_OFFSET(1),
> GEN7_SO_WRITE_OFFSET(2),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8e60737..533ec0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -427,6 +427,14 @@
> /* There are the 4 64-bit counter registers, one for each stream output */
> #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
>
> +#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
> +
> +#define GEN7_3DPRIM_START_VERTEX 0x2430
> +#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
> +#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
> +#define GEN7_3DPRIM_START_INSTANCE 0x243C
> +#define GEN7_3DPRIM_BASE_VERTEX 0x2440
> +
> #define OACONTROL 0x2360
>
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Add more registers to the whitelist for mesa
2014-04-08 21:18 [PATCH] drm/i915: Add more registers to the whitelist for mesa bradley.d.volkin
2014-04-09 13:34 ` Daniel Vetter
@ 2014-04-09 16:22 ` Kenneth Graunke
2014-04-09 16:46 ` Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Kenneth Graunke @ 2014-04-09 16:22 UTC (permalink / raw)
To: bradley.d.volkin, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2831 bytes --]
On 04/08/2014 02:18 PM, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> These are additional registers needed for performance monitoring and
> ARB_draw_indirect extensions in mesa.
Whoops...I totally missed this. Thanks!
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +++++++++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 29184d6..3486ef7 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -408,10 +408,19 @@ static const u32 gen7_render_regs[] = {
> REG64(PS_INVOCATION_COUNT),
> REG64(PS_DEPTH_COUNT),
> OACONTROL, /* Only allowed for LRI and SRM. See below. */
It would be great to add:
GEN7_3DPRIM_END_OFFSET,
which is the other ARB_draw_indirect register. I have no idea why we
don't use it - sure seems like we should...
> + GEN7_3DPRIM_START_VERTEX,
> + GEN7_3DPRIM_VERTEX_COUNT,
> + GEN7_3DPRIM_INSTANCE_COUNT,
> + GEN7_3DPRIM_START_INSTANCE,
> + GEN7_3DPRIM_BASE_VERTEX,
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
> REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
> + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
FWIW, I don't think we actually need to write these...we just read them.
Though, there's not much harm in it.
> GEN7_SO_WRITE_OFFSET(0),
> GEN7_SO_WRITE_OFFSET(1),
> GEN7_SO_WRITE_OFFSET(2),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8e60737..533ec0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -427,6 +427,14 @@
> /* There are the 4 64-bit counter registers, one for each stream output */
> #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
>
> +#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
> +
#define GEN7_3DPRIM_END_OFFSET 0x2420
> +#define GEN7_3DPRIM_START_VERTEX 0x2430
> +#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
> +#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
> +#define GEN7_3DPRIM_START_INSTANCE 0x243C
> +#define GEN7_3DPRIM_BASE_VERTEX 0x2440
> +
> #define OACONTROL 0x2360
>
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
With END_OFFSET added, this would get a:
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Add more registers to the whitelist for mesa
2014-04-09 16:22 ` Kenneth Graunke
@ 2014-04-09 16:46 ` Daniel Vetter
2014-04-09 17:12 ` [PATCH] SQUASH: drm/i915: One more register " bradley.d.volkin
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2014-04-09 16:46 UTC (permalink / raw)
To: Kenneth Graunke; +Cc: intel-gfx
On Wed, Apr 09, 2014 at 09:22:19AM -0700, Kenneth Graunke wrote:
> On 04/08/2014 02:18 PM, bradley.d.volkin@intel.com wrote:
> > From: Brad Volkin <bradley.d.volkin@intel.com>
> >
> > These are additional registers needed for performance monitoring and
> > ARB_draw_indirect extensions in mesa.
>
> Whoops...I totally missed this. Thanks!
>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719
> > Cc: Kenneth Graunke <kenneth@whitecape.org>
> > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 9 +++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 29184d6..3486ef7 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -408,10 +408,19 @@ static const u32 gen7_render_regs[] = {
> > REG64(PS_INVOCATION_COUNT),
> > REG64(PS_DEPTH_COUNT),
> > OACONTROL, /* Only allowed for LRI and SRM. See below. */
>
> It would be great to add:
>
> GEN7_3DPRIM_END_OFFSET,
>
> which is the other ARB_draw_indirect register. I have no idea why we
> don't use it - sure seems like we should...
>
> > + GEN7_3DPRIM_START_VERTEX,
> > + GEN7_3DPRIM_VERTEX_COUNT,
> > + GEN7_3DPRIM_INSTANCE_COUNT,
> > + GEN7_3DPRIM_START_INSTANCE,
> > + GEN7_3DPRIM_BASE_VERTEX,
> > REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
> > REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
> > REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
> > REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
> > + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
> > + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
> > + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
> > + REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
>
> FWIW, I don't think we actually need to write these...we just read them.
> Though, there's not much harm in it.
>
> > GEN7_SO_WRITE_OFFSET(0),
> > GEN7_SO_WRITE_OFFSET(1),
> > GEN7_SO_WRITE_OFFSET(2),
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8e60737..533ec0a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -427,6 +427,14 @@
> > /* There are the 4 64-bit counter registers, one for each stream output */
> > #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
> >
> > +#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
> > +
>
> #define GEN7_3DPRIM_END_OFFSET 0x2420
>
> > +#define GEN7_3DPRIM_START_VERTEX 0x2430
> > +#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
> > +#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
> > +#define GEN7_3DPRIM_START_INSTANCE 0x243C
> > +#define GEN7_3DPRIM_BASE_VERTEX 0x2440
> > +
> > #define OACONTROL 0x2360
> >
> > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
>
> With END_OFFSET added, this would get a:
> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brad I've already pulled this in for my rebasing tree to unblock mesa
testing. Feel free to either supply a fixup for me to squash in or a
replacement patch, I can handle either.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH] SQUASH: drm/i915: One more register for mesa
2014-04-09 16:46 ` Daniel Vetter
@ 2014-04-09 17:12 ` bradley.d.volkin
2014-04-09 19:54 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: bradley.d.volkin @ 2014-04-09 17:12 UTC (permalink / raw)
To: intel-gfx
From: Brad Volkin <bradley.d.volkin@intel.com>
Originally left out because it wasn't used. But it may be needed
and doesn't pose any risk, so add to the whitelist.
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 3486ef7..9bac097 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -408,6 +408,7 @@ static const u32 gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
OACONTROL, /* Only allowed for LRI and SRM. See below. */
+ GEN7_3DPRIM_END_OFFSET,
GEN7_3DPRIM_START_VERTEX,
GEN7_3DPRIM_VERTEX_COUNT,
GEN7_3DPRIM_INSTANCE_COUNT,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f49569b..46ea233 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -430,6 +430,7 @@
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
+#define GEN7_3DPRIM_END_OFFSET 0x2420
#define GEN7_3DPRIM_START_VERTEX 0x2430
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] SQUASH: drm/i915: One more register for mesa
2014-04-09 17:12 ` [PATCH] SQUASH: drm/i915: One more register " bradley.d.volkin
@ 2014-04-09 19:54 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-04-09 19:54 UTC (permalink / raw)
To: bradley.d.volkin; +Cc: intel-gfx
On Wed, Apr 09, 2014 at 10:12:54AM -0700, bradley.d.volkin@intel.com wrote:
> From: Brad Volkin <bradley.d.volkin@intel.com>
>
> Originally left out because it wasn't used. But it may be needed
> and doesn't pose any risk, so add to the whitelist.
>
> Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Fixup squashed in, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 3486ef7..9bac097 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -408,6 +408,7 @@ static const u32 gen7_render_regs[] = {
> REG64(PS_INVOCATION_COUNT),
> REG64(PS_DEPTH_COUNT),
> OACONTROL, /* Only allowed for LRI and SRM. See below. */
> + GEN7_3DPRIM_END_OFFSET,
> GEN7_3DPRIM_START_VERTEX,
> GEN7_3DPRIM_VERTEX_COUNT,
> GEN7_3DPRIM_INSTANCE_COUNT,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f49569b..46ea233 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -430,6 +430,7 @@
>
> #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
>
> +#define GEN7_3DPRIM_END_OFFSET 0x2420
> #define GEN7_3DPRIM_START_VERTEX 0x2430
> #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
> #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-04-08 21:18 [PATCH] drm/i915: Add more registers to the whitelist for mesa bradley.d.volkin
2014-04-09 13:34 ` Daniel Vetter
2014-04-09 16:22 ` Kenneth Graunke
2014-04-09 16:46 ` Daniel Vetter
2014-04-09 17:12 ` [PATCH] SQUASH: drm/i915: One more register " bradley.d.volkin
2014-04-09 19:54 ` Daniel Vetter
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