From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak S Subject: Re: [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff Date: Thu, 10 Apr 2014 00:08:07 +0530 Message-ID: <5345938F.2030905@linux.intel.com> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-46-git-send-email-ville.syrjala@linux.intel.com> <20140409160236.GO9262@phenom.ffwll.local> <20140409174749.GU18465@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DE7E6E0DB for ; Wed, 9 Apr 2014 11:38:10 -0700 (PDT) In-Reply-To: <20140409174749.GU18465@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= , Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wednesday 09 April 2014 11:17 PM, Ville Syrj=E4l=E4 wrote: > On Wed, Apr 09, 2014 at 06:02:36PM +0200, Daniel Vetter wrote: >> On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrjala@linux.intel.com = wrote: >>> From: Ville Syrj=E4l=E4 >>> >>> Streamline the CHV forcewake functions just like was done for VLV. >>> >>> This will also fix a bug in accessing the common well registers, >>> where we'd end up trying to wake up the wells too many times >>> since we'd call force_wake_get/put twice per register access, with >>> FORCEFAKE_ALL both times. >>> >>> Reviewed-by: Mika Kuoppala >>> Signed-off-by: Ville Syrj=E4l=E4 >> Ugh ... any chance this would make sense squashed in as a fixup into an >> earlier patch? If it's too hairy I'm ok with this as-is. > It could be squashed into patch 28 which introduces this code. I don't > think there were other patches that touch this piece code. I have no > objection to squashing. Deepak, any objections? Nope. I am Ok with squashing the patch. >> -Daniel >> >>> --- >>> drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++--------------= --------- >>> 1 file changed, 32 insertions(+), 56 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915= /intel_uncore.c >>> index ccad770..59293b3 100644 >>> --- a/drivers/gpu/drm/i915/intel_uncore.c >>> +++ b/drivers/gpu/drm/i915/intel_uncore.c >>> @@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, of= f_t reg, bool trace) { \ >>> unsigned fwengine =3D 0; \ >>> REG_READ_HEADER(x); \ >>> if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_RENDER; \ >>> - } \ >>> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_MEDIA; \ >>> - } \ >>> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_ALL; \ >>> - } \ >>> - if (FORCEWAKE_RENDER & fwengine) { \ >>> - if (dev_priv->uncore.fw_rendercount++ =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> - if (FORCEWAKE_MEDIA & fwengine) { \ >>> - if (dev_priv->uncore.fw_mediacount++ =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ >>> - fwengine); \ >>> + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> + fwengine =3D FORCEWAKE_RENDER; \ >>> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ >>> + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> + fwengine =3D FORCEWAKE_MEDIA; \ >>> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ >>> + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> + fwengine |=3D FORCEWAKE_RENDER; \ >>> + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> + fwengine |=3D FORCEWAKE_MEDIA; \ >>> } \ >>> + if (fwengine) \ >>> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ >>> val =3D __raw_i915_read##x(dev_priv, reg); \ >>> - if (FORCEWAKE_RENDER & fwengine) { \ >>> - if (--dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> - if (FORCEWAKE_MEDIA & fwengine) { \ >>> - if (--dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> + if (fwengine) \ >>> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ >>> REG_READ_FOOTER; \ >>> } >>> = >>> @@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, = off_t reg, u##x val, bool trace >>> static void \ >>> chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, = bool trace) { \ >>> unsigned fwengine =3D 0; \ >>> - bool __needs_put =3D !is_gen8_shadowed(dev_priv, reg); \ >>> + bool shadowed =3D is_gen8_shadowed(dev_priv, reg); \ >>> REG_WRITE_HEADER; \ >>> - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_RENDER; \ >>> - } \ >>> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_MEDIA; \ >>> - } \ >>> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ >>> - fwengine =3D FORCEWAKE_ALL; \ >>> - } \ >>> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ >>> - if (dev_priv->uncore.fw_rendercount++ =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ >>> - if (dev_priv->uncore.fw_mediacount++ =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ >>> - fwengine); \ >>> + if (!shadowed) { \ >>> + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ >>> + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> + fwengine =3D FORCEWAKE_RENDER; \ >>> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ >>> + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> + fwengine =3D FORCEWAKE_MEDIA; \ >>> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ >>> + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> + fwengine |=3D FORCEWAKE_RENDER; \ >>> + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> + fwengine |=3D FORCEWAKE_MEDIA; \ >>> + } \ >>> } \ >>> + if (fwengine) \ >>> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ >>> __raw_i915_write##x(dev_priv, reg, val); \ >>> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ >>> - if (--dev_priv->uncore.fw_rendercount =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ >>> - if (--dev_priv->uncore.fw_mediacount =3D=3D 0) \ >>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ >>> - fwengine); \ >>> - } \ >>> + if (fwengine) \ >>> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ >>> REG_WRITE_FOOTER; \ >>> } >>> = >>> -- = >>> 1.8.3.2 >>> >>> _______________________________________________ >>> Intel-gfx mailing list >>> Intel-gfx@lists.freedesktop.org >>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> -- = >> Daniel Vetter >> Software Engineer, Intel Corporation >> +41 (0) 79 365 57 48 - http://blog.ffwll.ch