Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

Ville Syrjälä
2014-04-09T13:15:53Z

On Wed, Apr 09, 2014 at 02:06:54PM +0100, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
> > +static void gen8_enable_rps_interrupts(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + /* Clear out any stale interrupts first */
> > + spin_lock_irq(&dev_priv->irq_lock);
> > + WARN_ON(dev_priv->rps.pm_iir);
> > + I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
> > + dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
> > + I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
> > + spin_unlock_irq(&dev_priv->irq_lock);
> > +
> > + I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
> > + /* only unmask PM interrupts we need. Mask all others. */
> > + I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
>
> PMINTRMSK handling is now a part of set_rps (and so this line is
> redundant).

Yeah there's been a lot of churn in this area recently and these patches
were written quite a while ago. I must admit I've not followed the recent
changes too closely, so I'm hoping Deepak will take the ball here and
massage this stuff until it fits in with the current code.

--
Ville Syrjälä
Intel OTC