Re: [PATCH v2 09/71] drm/i915/chv: Add DPINVGTT registers defines for Cherryview

Daniel Vetter
2014-05-06T19:20:34Z

On Fri, May 02, 2014 at 11:35:51AM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Due to Pipe C DPINVGTT has more bits on CHV.
>
> v2: Fix comment to say VLV/CHV (Rafael)
>
> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Merged up to this one to dinq.
-Daniel

> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 12fa93a..666c1d0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3494,7 +3494,11 @@ enum punit_power_well {
> #define SPRITEE_FLIPDONE_INT_EN (1<<9)
> #define PLANEC_FLIPDONE_INT_EN (1<<8)
>
> -#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
> +#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
> +#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
> +#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
> +#define PLANEC_INVALID_GTT_INT_EN (1<<25)
> +#define CURSORC_INVALID_GTT_INT_EN (1<<24)
> #define CURSORB_INVALID_GTT_INT_EN (1<<23)
> #define CURSORA_INVALID_GTT_INT_EN (1<<22)
> #define SPRITED_INVALID_GTT_INT_EN (1<<21)
> @@ -3504,6 +3508,11 @@ enum punit_power_well {
> #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
> #define PLANEA_INVALID_GTT_INT_EN (1<<16)
> #define DPINVGTT_EN_MASK 0xff0000
> +#define DPINVGTT_EN_MASK_CHV 0xfff0000
> +#define SPRITEF_INVALID_GTT_STATUS (1<<11)
> +#define SPRITEE_INVALID_GTT_STATUS (1<<10)
> +#define PLANEC_INVALID_GTT_STATUS (1<<9)
> +#define CURSORC_INVALID_GTT_STATUS (1<<8)
> #define CURSORB_INVALID_GTT_STATUS (1<<7)
> #define CURSORA_INVALID_GTT_STATUS (1<<6)
> #define SPRITED_INVALID_GTT_STATUS (1<<5)
> @@ -3513,6 +3522,7 @@ enum punit_power_well {
> #define SPRITEA_INVALID_GTT_STATUS (1<<1)
> #define PLANEA_INVALID_GTT_STATUS (1<<0)
> #define DPINVGTT_STATUS_MASK 0xff
> +#define DPINVGTT_STATUS_MASK_CHV 0xfff
>
> #define DSPARB 0x70030
> #define DSPARB_CSTART_MASK (0x7f << 7)
> --
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch