From mboxrd@z Thu Jan  1 00:00:00 1970
From: Deepak S <deepak.s@linux.intel.com>
Subject: Re: [PATCH 30/71] drm/i915/chv: Enable PM interrupts
 when we in CHV turbo initialize sequence.
Date: Thu, 10 Apr 2014 00:47:01 +0530
Message-ID: <53459CAD.9060102@linux.intel.com>
References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com>
 <1397039349-10639-31-git-send-email-ville.syrjala@linux.intel.com>
 <20140409130654.GA4573@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; Format="flowed"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
 by gabe.freedesktop.org (Postfix) with ESMTP id 6D05A6EBBD
 for <intel-gfx@lists.freedesktop.org>; Wed,  9 Apr 2014 12:17:10 -0700 (PDT)
In-Reply-To: <20140409130654.GA4573@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org


On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala@linux.intel.com wrote:
>> +static void gen8_enable_rps_interrupts(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> +	/* Clear out any stale interrupts first */
>> +	spin_lock_irq(&dev_priv->irq_lock);
>> +	WARN_ON(dev_priv->rps.pm_iir);
>> +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
>> +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
>> +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
>> +	spin_unlock_irq(&dev_priv->irq_lock);
>> +
>> +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
>> +	/* only unmask PM interrupts we need. Mask all others. */
>> +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> PMINTRMSK handling is now a part of set_rps (and so this line is
> redundant).
> -Chris

Thanks Chris. I will make the changes based on the current nightly code