* [PATCH 00/10] Enable RC6/Turbo on CHV
@ 2014-04-21 7:53 deepak.s
2014-04-21 13:58 ` Deepak S
0 siblings, 1 reply; 6+ messages in thread
From: deepak.s @ 2014-04-21 7:53 UTC (permalink / raw)
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
Squashed some of the patches and created a new patch series.
ToDo: Address the comments on some the patches. Changes will be shared in next series.
Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler
Deepak S (6):
drm/i915: Enable PM Interrupts target via Display Interface.
drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
drm/i915/chv: Added CHV specific register read and write
drm/i915/chv: Enable RPS (Turbo) for Cheeryview
drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
drm/i915/chv: Freq(opcode) request value for CHV.
Ville Syrjälä (3):
drm/i915/chv: Streamline CHV forcewake stuff
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_irq.c | 79 +++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 13 ++
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 231 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 15 +++
drivers/gpu/drm/i915/intel_uncore.c | 126 +++++++++++++++++--
7 files changed, 455 insertions(+), 21 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 00/10] Enable RC6/Turbo on CHV
2014-04-21 7:53 [PATCH 00/10] Enable RC6/Turbo on CHV deepak.s
@ 2014-04-21 13:58 ` Deepak S
2014-04-22 20:19 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Deepak S @ 2014-04-21 13:58 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
Hi Ville,
let me know if you want some of other small patches to be squashed.
Thanks
Deepak
On Monday 21 April 2014 01:23 PM, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> Squashed some of the patches and created a new patch series.
>
> ToDo: Address the comments on some the patches. Changes will be shared in next series.
>
> Ben Widawsky (1):
> drm/i915/bdw: Implement a basic PM interrupt handler
>
> Deepak S (6):
> drm/i915: Enable PM Interrupts target via Display Interface.
> drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
> drm/i915/chv: Added CHV specific register read and write
> drm/i915/chv: Enable RPS (Turbo) for Cheeryview
> drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
> drm/i915/chv: Freq(opcode) request value for CHV.
>
> Ville Syrjälä (3):
> drm/i915/chv: Streamline CHV forcewake stuff
> drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
> drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
>
> drivers/gpu/drm/i915/i915_drv.h | 10 ++
> drivers/gpu/drm/i915/i915_irq.c | 79 +++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 13 ++
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_pm.c | 231 +++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_sideband.c | 15 +++
> drivers/gpu/drm/i915/intel_uncore.c | 126 +++++++++++++++++--
> 7 files changed, 455 insertions(+), 21 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 00/10] Enable RC6/Turbo on CHV
2014-04-21 13:58 ` Deepak S
@ 2014-04-22 20:19 ` Daniel Vetter
2014-04-23 5:09 ` Deepak S
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2014-04-22 20:19 UTC (permalink / raw)
To: Deepak S; +Cc: intel-gfx
On Mon, Apr 21, 2014 at 07:28:54PM +0530, Deepak S wrote:
> Hi Ville,
>
> let me know if you want some of other small patches to be squashed.
Quick aside: Something seems to have gone with git send-email thread - the
patches aren't in-reply-to the cover letter. No idea how that happened
though ...
-Daniel
>
> Thanks
> Deepak
>
>
> On Monday 21 April 2014 01:23 PM, deepak.s@linux.intel.com wrote:
> >From: Deepak S <deepak.s@linux.intel.com>
> >
> >Squashed some of the patches and created a new patch series.
> >
> >ToDo: Address the comments on some the patches. Changes will be shared in next series.
> >
> >Ben Widawsky (1):
> > drm/i915/bdw: Implement a basic PM interrupt handler
> >
> >Deepak S (6):
> > drm/i915: Enable PM Interrupts target via Display Interface.
> > drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
> > drm/i915/chv: Added CHV specific register read and write
> > drm/i915/chv: Enable RPS (Turbo) for Cheeryview
> > drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
> > drm/i915/chv: Freq(opcode) request value for CHV.
> >
> >Ville Syrjälä (3):
> > drm/i915/chv: Streamline CHV forcewake stuff
> > drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
> > drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
> >
> > drivers/gpu/drm/i915/i915_drv.h | 10 ++
> > drivers/gpu/drm/i915/i915_irq.c | 79 +++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 13 ++
> > drivers/gpu/drm/i915/intel_drv.h | 2 +
> > drivers/gpu/drm/i915/intel_pm.c | 231 +++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_sideband.c | 15 +++
> > drivers/gpu/drm/i915/intel_uncore.c | 126 +++++++++++++++++--
> > 7 files changed, 455 insertions(+), 21 deletions(-)
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 00/10] Enable RC6/Turbo on CHV
2014-04-22 20:19 ` Daniel Vetter
@ 2014-04-23 5:09 ` Deepak S
0 siblings, 0 replies; 6+ messages in thread
From: Deepak S @ 2014-04-23 5:09 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wednesday 23 April 2014 01:49 AM, Daniel Vetter wrote:
> On Mon, Apr 21, 2014 at 07:28:54PM +0530, Deepak S wrote:
>> Hi Ville,
>>
>> let me know if you want some of other small patches to be squashed.
> Quick aside: Something seems to have gone with git send-email thread - the
> patches aren't in-reply-to the cover letter. No idea how that happened
> though ...
> -Daniel
Not Sure :( I can resend the patches again
>> Thanks
>> Deepak
>>
>>
>> On Monday 21 April 2014 01:23 PM, deepak.s@linux.intel.com wrote:
>>> From: Deepak S <deepak.s@linux.intel.com>
>>>
>>> Squashed some of the patches and created a new patch series.
>>>
>>> ToDo: Address the comments on some the patches. Changes will be shared in next series.
>>>
>>> Ben Widawsky (1):
>>> drm/i915/bdw: Implement a basic PM interrupt handler
>>>
>>> Deepak S (6):
>>> drm/i915: Enable PM Interrupts target via Display Interface.
>>> drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
>>> drm/i915/chv: Added CHV specific register read and write
>>> drm/i915/chv: Enable RPS (Turbo) for Cheeryview
>>> drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
>>> drm/i915/chv: Freq(opcode) request value for CHV.
>>>
>>> Ville Syrjälä (3):
>>> drm/i915/chv: Streamline CHV forcewake stuff
>>> drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
>>> drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
>>>
>>> drivers/gpu/drm/i915/i915_drv.h | 10 ++
>>> drivers/gpu/drm/i915/i915_irq.c | 79 +++++++++++-
>>> drivers/gpu/drm/i915/i915_reg.h | 13 ++
>>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>>> drivers/gpu/drm/i915/intel_pm.c | 231 +++++++++++++++++++++++++++++++++-
>>> drivers/gpu/drm/i915/intel_sideband.c | 15 +++
>>> drivers/gpu/drm/i915/intel_uncore.c | 126 +++++++++++++++++--
>>> 7 files changed, 455 insertions(+), 21 deletions(-)
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 00/10] Enable RC6/Turbo on CHV
@ 2014-05-05 12:47 deepak.s
2014-05-15 21:22 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: deepak.s @ 2014-05-05 12:47 UTC (permalink / raw)
To: intel-gfx; +Cc: fafael.barbalho
From: Deepak S <deepak.s@linux.intel.com>
Squashed some of the patches and created a new patch series. Addressed review comments on most of the patches.
Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler
Deepak S (7):
drm/i915: Enable PM Interrupts target via Display Interface.
drm/i915/chv: Enable Render Standby (RC6) for Cherryview
drm/i915/chv: Added CHV specific register read and write
drm/i915/chv: Streamline CHV forcewake stuff
drm/i915/chv: Enable RPS (Turbo) for Cherryview
drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
drm/i915/chv: Freq(opcode) request for CHV.
Ville Syrjälä (2):
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 84 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 17 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 259 ++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_uncore.c | 146 ++++++++++++++++---
7 files changed, 491 insertions(+), 34 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 00/10] Enable RC6/Turbo on CHV
2014-05-05 12:47 deepak.s
@ 2014-05-15 21:22 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-05-15 21:22 UTC (permalink / raw)
To: deepak.s; +Cc: intel-gfx, fafael.barbalho
On Mon, May 05, 2014 at 06:17:29PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> Squashed some of the patches and created a new patch series. Addressed review comments on most of the patches.
>
> Ben Widawsky (1):
> drm/i915/bdw: Implement a basic PM interrupt handler
>
> Deepak S (7):
> drm/i915: Enable PM Interrupts target via Display Interface.
> drm/i915/chv: Enable Render Standby (RC6) for Cherryview
> drm/i915/chv: Added CHV specific register read and write
> drm/i915/chv: Streamline CHV forcewake stuff
> drm/i915/chv: Enable RPS (Turbo) for Cherryview
> drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
> drm/i915/chv: Freq(opcode) request for CHV.
>
> Ville Syrjälä (2):
> drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
> drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
Just for coordination: I've just pulled in the bdw-only series from Mika,
so I guess you need to rebase the chv patches on top of drm-intel-nightly.
I think -nightly has now enough of the chv stuff merged that this should
work out. Otherwise I need to beat up the reviewers to not slack off this
much :(
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-04-21 7:53 [PATCH 00/10] Enable RC6/Turbo on CHV deepak.s
2014-04-21 13:58 ` Deepak S
2014-04-22 20:19 ` Daniel Vetter
2014-04-23 5:09 ` Deepak S
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2014-05-15 21:22 ` Daniel Vetter
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