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From: Deepak S <deepak.s@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>, Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview
Date: Mon, 28 Apr 2014 20:32:00 +0530	[thread overview]
Message-ID: <535E6D68.10703@linux.intel.com> (raw)
In-Reply-To: <20140428144532.GF32404@phenom.ffwll.local>


On Monday 28 April 2014 08:15 PM, Daniel Vetter wrote:
> On Mon, Apr 28, 2014 at 05:29:46PM +0300, Imre Deak wrote:
>>> +static void cherryview_setup_pctx(struct drm_device *dev)
>>> +{
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +	unsigned long pctx_paddr;
>>> +	struct i915_gtt *gtt = &dev_priv->gtt;
>>> +	u32 pcbr;
>>> +	int pctx_size = 32*1024;
>>> +
>>> +	pcbr = I915_READ(VLV_PCBR);
>>> +	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
>>> +		/*
>>> +		 * From the Gunit register HAS:
>>> +		 * The Gfx driver is expected to program this register and ensure
>>> +		 * proper allocation within Gfx stolen memory.  For example, this
>>> +		 * register should be programmed such than the PCBR range does not
>>> +		 * overlap with other relevant ranges.
>>> +		 */
>>> +		pctx_paddr = (dev_priv->mm.stolen_base + gtt->stolen_size - pctx_size);
>> This area should be reserved.
> We've had a really lengthy discussion internally about the bios-reserved
> chunk in stolen. It was stalled due to (imo unjustified) fear to leak
> information what the bios actually uses this for.
>
> If we need to reserve more of stolen than we currently do we need to pick
> up that approach again instead of adding more bandaids.
> -Daniel

Agreed. Will change accordingly.

  reply	other threads:[~2014-04-28 15:06 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-21  8:04 [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler deepak.s
2014-04-21  8:04 ` [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface deepak.s
2014-04-25 21:33   ` Ben Widawsky
2014-04-21  8:04 ` [PATCH 03/10] drm/i915/chv: Enable Render Standby (RC6) for Cheeryview deepak.s
2014-04-25 21:42   ` Ben Widawsky
2014-04-25 21:44     ` Ben Widawsky
2014-04-28 15:11     ` Deepak S
2014-04-28 14:29   ` Imre Deak
2014-04-28 14:45     ` Daniel Vetter
2014-04-28 15:02       ` Deepak S [this message]
2014-04-28 15:10     ` Deepak S
2014-04-21  8:04 ` [PATCH 04/10] drm/i915/chv: Added CHV specific register read and write deepak.s
2014-04-25 21:54   ` Ben Widawsky
2014-05-05  5:55     ` Deepak S
2014-04-21  8:04 ` [PATCH 05/10] drm/i915/chv: Enable RPS (Turbo) for Cheeryview deepak.s
2014-04-25 22:17   ` Ben Widawsky
2014-04-21  8:04 ` [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff deepak.s
2014-04-25 22:24   ` Ben Widawsky
2014-04-21  8:04 ` [PATCH 07/10] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-04-21  8:04 ` [PATCH 08/10] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-04-25 22:26   ` Ben Widawsky
2014-04-21  8:04 ` [PATCH 09/10] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-04-25 22:28   ` Ben Widawsky
2014-04-21  8:04 ` [PATCH 10/10] drm/i915/chv: Freq(opcode) request value for CHV deepak.s
2014-04-25 22:32   ` Ben Widawsky
2014-04-25 21:08 ` [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler Ben Widawsky

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