From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Richter Subject: Re: 830GM still woes Date: Sat, 17 May 2014 12:58:50 +0200 Message-ID: <537740EA.4070104@math.tu-berlin.de> References: <53761A88.1060608@math.tu-berlin.de> <20140516144104.GE3473@nuc-i3427.alporthouse.com> <20140516150953.GN8790@phenom.ffwll.local> <20140516160454.GT27580@intel.com> <23914_1400259040_537641E0_23914_9298_1_20140516165034.GT8790@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-2.alumni.tu-berlin.de (mail-2.alumni.tu-berlin.de [130.149.5.29]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AE0D6E352 for ; Sat, 17 May 2014 04:07:56 -0700 (PDT) In-Reply-To: <23914_1400259040_537641E0_23914_9298_1_20140516165034.GT8790@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter , =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org Am 16.05.2014 18:50, schrieb Daniel Vetter: > On Fri, May 16, 2014 at 07:04:54PM +0300, Ville Syrj=E4l=E4 wrote: >> On Fri, May 16, 2014 at 05:09:53PM +0200, Daniel Vetter wrote: >>> On Fri, May 16, 2014 at 03:41:05PM +0100, Chris Wilson wrote: >>>> On Fri, May 16, 2014 at 04:02:48PM +0200, Thomas Richter wrote: >>>>> It's not that I haven't had a patch for it. Really trivial. I wonder >>>>> what keeps you from adding this to the kernel and just make things >>>>> working? >>>> >>>> You mean this patch? >>>> >>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in= tel_pm.c >>>> index f671aca..3981898 100644 >>>> --- a/drivers/gpu/drm/i915/intel_pm.c >>>> +++ b/drivers/gpu/drm/i915/intel_pm.c >>>> @@ -944,7 +944,7 @@ static const struct intel_watermark_params i915_wm= _info =3D { >>>> static const struct intel_watermark_params i830_wm_info =3D { >>>> I855GM_FIFO_SIZE, >>>> I915_MAX_WM, >>>> - 1, >>>> + 8, >>>> 2, >>>> I830_FIFO_LINE_SIZE >>>> }; >>>> @@ -1001,7 +1001,7 @@ static unsigned long intel_calculate_wm(unsigned= long clock_in_khz, >>>> /* Don't promote wm_size to unsigned... */ >>>> if (wm_size > (long)wm->max_wm) >>>> wm_size =3D wm->max_wm; >>>> - if (wm_size <=3D 0) >>>> + if (wm_size < (long)wm->default_wm) >>>> wm_size =3D wm->default_wm; >>>> return wm_size; >>>> } For example. There are a couple of possibilities to add this. If this is = too invasive, it is not too hard to add a similar check to = i9xx_update_wm for generation 2 only, and enforce the same type of check = to i830_update_wm >> On Gen3 the units change to 64B but it still has the same note with >> the +32B, so I'm not sure what should be done there. I guess it's >> just a copy paste fumble and maybe the same minimum value should >> still apply. > > Yeah the burst size stuff - afaiu we should select the biggest one > possible and if that's not working out round the watermark up to match the > burst size. I didn't spot the +32/-32bytes anywhere though ... I guess > going with burst_size + 1 should be safest, especially if we make the code > more flexible to also allow a burst size of 4 for the really high-res > stuff. This would be highly appreciated, yes. I currently constantly patch my = kernel to keep the graphics working, but that's please not a permanent = solution. Thank you, and have a nice weekend. Greetings, Thomas