[PATCH 00/66] runtime pm for DPMS

[PATCH 00/66] runtime pm for DPMS

[Daniel Vetter]

Hi all,

So this is a little patch series that started very innocently as a small cleanup
in prep for some of the bigger features and then got out of hand. It now
implements runtime pm support for DPMS on everything that supports it.

Still rather lightly tested because of too many distractions this week.

After this series all the hw enabling is _only_ done in the ->enable hooks.
Encoder ->mode_set callbacks are completely gone and the crtc mode_set hooks
only do some pll state computations. This is a nice prep for atomic modesets too
since now all remaining code in the crtc mode_set callbacks must be moved out
into the preparatory compute_config stage. Unfortunately the code is tricky and
also depends upon the entire hw/sw state in tricky ways.

Anyway the entire pile nicely splits into sub-series, see below for in-line
comments.

Feedback and also testing from untime pm experts highly welcome. Presuming no
fundamental issues I'll sign up people for in-depth reviews soonish.

Cheers, Daniel

Daniel Vetter (66):
  drm/i915: Make encoder->mode_set callbacks optional
  drm/i915/dvo: Remove ->mode_set callback
  drm/i915/tv: extract set_tv_mode_timings
  drm/i915/tv: extract set_color_conversion
  drm/i915/tv: De-magic device check
  drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
  drm/i915/tv: Remove ->mode_set callback
  drm/i915/crt: Remove ->mode_set callback
  drm/i915/sdvo: Remove ->mode_set callback

Removal of encoder->mode_set callbacks, part 1

  drm/i915/hdmi: Enable hdmi mode on g4x, too
  drm/i915: Track hdmi mode in the pipe config
  drm/i915/sdvo: Use pipe_config->limited_color_range consistently
  drm/i915: state readout and cross checking for limited_color_range
  drm/i915/sdvo: use config->has_hdmi_sink
  drm/i915: Simplify audio handling on DDI ports
  drm/i915: Track has_audio in the pipe config
  drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
  drm/i915/dp: Remove ->mode_set callback
  drm/i915/hdmi: Remove redundant IS_VLV checks
  drm/i915/hdmi: Remove ->mode_set callback

Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
interludes to move a bit of the hdmi/audio state into the pipe config.

  drm/i915/lvds: Remove ->mode_set callback
  drm/i915/ddi: Remove ->mode_set callback
  drm/i915/dsi: Remove ->mode_set callback
  drm/i915: Stop calling encoder->mode_set

Final removals of encoder->mode_set callbacks

  drm/i915: Make ->update_primary_plane infallible
  drm/i915: More cargo-culted locking for intel_update_fbc
  drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
  drm/i915: Inline set_base into crtc_mode_set
  drm/i915: Move fb pinning into __intel_set_mode

Some shuffling to get the primary->fb handling out of crtc mode_set callbacks

  drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
  drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
  drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
  drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
  drm/i915: Extract i9xx_set_pll_dividers
  drm/i915: Extract vlv_prepare_pll

gmch pll moved out of crtc mode_set callbacks into ->enable hooks

  drm/i915: Only update shared dpll state when needed
  drm/i915: Extract intel_prepare_shared_dpll
  drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

Prep polish on the existing shared_dpll code

  drm/i915: Check hw state in assert_can_disable_lcpll
  drm/i915: Remove spll_refcount for hsw
  drm/i915: Clean up WRPLL/SPLL #defines
  drm/i915: Make intel_wait_for_pipe_off static
  drm/i915: Disable pipe before ports on ilk
  drm/i915: Pass port explicitly to intel_ddi_get_hw_state
  drm/i915: Unexport intel_ddi_connector_get_hw_state
  drm/i915: Move hsw_fdi_link_train into intel_crt.c
  drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
  drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
  drm/i915: Move lpt_pch_enable int hsw_crt_enable
  drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
  drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
  drm/i915: Move pch fifo underrun report re-enabling into
    hsw_crt_post_disable
  drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
  drm/i915: Move SPLL disabling into hsw_crt_post_disable

Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
on haswell. This has the nice upshot to make SPLL logically a port-private clock
and so removes it from further considerations.

  drm/i915: Add a debugfs file for the shared dpll state
  drm/i915: Move ddi_pll_sel into the pipe config
  drm/i915: State readout and cross-checking for ddi_pll_sel
  drm/i915: Precompute static ddi_pll_sel values in encoders
  drm/i915: Basic shared dpll support for WRPLLs
  drm/i915: Document that the pll->mode_set hook is optional
  drm/i915: State readout support for WRPLLs
  drm/i915: ->disable hook for WRPLLs
  drm/i915: ->enable hook for WRPLLs
  drm/i915: Switch to common shared dpll framework for WRPLLs
  drm/i915: Only touch WRPLL hw state in enable/disable hooks

Convert wrpll handling to the common shared_dpll framework. We need this since
runtime pm for dpms requires us to separately track pll refernces from crtcs and
active usage by crtcs

  drm/i915: runtime PM support for DPMS

The final piece.

 drivers/gpu/drm/i915/i915_debugfs.c  |  27 ++
 drivers/gpu/drm/i915/i915_drv.h      |  22 +-
 drivers/gpu/drm/i915/i915_reg.h      |  10 +-
 drivers/gpu/drm/i915/intel_crt.c     | 456 ++++++++++++++++++---
 drivers/gpu/drm/i915/intel_ddi.c     | 609 ++++++----------------------
 drivers/gpu/drm/i915/intel_display.c | 747 ++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_dp.c      |  51 ++-
 drivers/gpu/drm/i915/intel_drv.h     |  47 ++-
 drivers/gpu/drm/i915/intel_dsi.c     |  19 +-
 drivers/gpu/drm/i915/intel_dvo.c     |   4 +-
 drivers/gpu/drm/i915/intel_hdmi.c    |  63 +--
 drivers/gpu/drm/i915/intel_lvds.c    |  14 -
 drivers/gpu/drm/i915/intel_sdvo.c    |  37 +-
 drivers/gpu/drm/i915/intel_tv.c      | 214 +++++-----
 14 files changed, 1153 insertions(+), 1167 deletions(-)

-- 
1.8.1.4

[PATCH 01/66] drm/i915: Make encoder->mode_set callbacks optional

[Daniel Vetter]

For a bunch of reasons we want to move away from the ->mode_set
callbacks: All hw state setup needs to move into ->enable hooks (so
that DOMS can do runtime pm) and all the configuration setup needs to
move into the compute_config functions.

To start with this make the enocer->mode_set callback optional.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b57210c52f00..5fed7aaf879d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7219,7 +7219,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			encoder->base.base.id,
 			drm_get_encoder_name(&encoder->base),
 			mode->base.id, mode->name);
-		encoder->mode_set(encoder);
+
+		if (encoder->mode_set)
+			encoder->mode_set(encoder);
 	}
 
 	return 0;
-- 
1.8.1.4

[PATCH 02/66] drm/i915/dvo: Remove ->mode_set callback

[Daniel Vetter]

Currently for the i9xx crtc hooks there's nothing between the call to
encoder->mode_set and encoder->pre_enable which touches the hardware.

Therefore, since dvo is only used on gen2, we can just move the hook.
Yay for easy cases!

The only other important thing to check is that the new
->pre_enable hook is idempotent wrt the sw state since now it can be
called multiple times (due to DPMS). It only reads crtc->config but
otherwise leaves it as-is, so we're good.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_dvo.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 7fe3feedfe03..1604235d58e6 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -285,7 +285,7 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
-static void intel_dvo_mode_set(struct intel_encoder *encoder)
+static void intel_dvo_pre_enable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -475,7 +475,7 @@ void intel_dvo_init(struct drm_device *dev)
 	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
 	intel_encoder->get_config = intel_dvo_get_config;
 	intel_encoder->compute_config = intel_dvo_compute_config;
-	intel_encoder->mode_set = intel_dvo_mode_set;
+	intel_encoder->pre_enable = intel_dvo_pre_enable;
 	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
 	intel_connector->unregister = intel_connector_unregister;
 
-- 
1.8.1.4

[PATCH 03/66] drm/i915/tv: extract set_tv_mode_timings

[Daniel Vetter]

intel_tv_mode_set is just too big.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_tv.c | 111 ++++++++++++++++++++++------------------
 1 file changed, 61 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index bafe92e317d5..04bf8caaac0c 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -934,6 +934,65 @@ intel_tv_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void
+set_tv_mode_timings(struct drm_i915_private *dev_priv,
+		    const struct tv_mode *tv_mode,
+		    bool burst_ena)
+{
+	u32 hctl1, hctl2, hctl3;
+	u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
+
+	hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
+		(tv_mode->htotal << TV_HTOTAL_SHIFT);
+
+	hctl2 = (tv_mode->hburst_start << 16) |
+		(tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
+
+	if (burst_ena)
+		hctl2 |= TV_BURST_ENA;
+
+	hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
+		(tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
+
+	vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
+		(tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
+		(tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
+
+	vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
+		(tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
+		(tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
+
+	vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
+		(tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
+		(tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
+
+	if (tv_mode->veq_ena)
+		vctl3 |= TV_EQUAL_ENA;
+
+	vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
+		(tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
+
+	vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
+		(tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
+
+	vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
+		(tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
+
+	vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
+		(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
+
+	I915_WRITE(TV_H_CTL_1, hctl1);
+	I915_WRITE(TV_H_CTL_2, hctl2);
+	I915_WRITE(TV_H_CTL_3, hctl3);
+	I915_WRITE(TV_V_CTL_1, vctl1);
+	I915_WRITE(TV_V_CTL_2, vctl2);
+	I915_WRITE(TV_V_CTL_3, vctl3);
+	I915_WRITE(TV_V_CTL_4, vctl4);
+	I915_WRITE(TV_V_CTL_5, vctl5);
+	I915_WRITE(TV_V_CTL_6, vctl6);
+	I915_WRITE(TV_V_CTL_7, vctl7);
+}
+
 static void intel_tv_mode_set(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
@@ -942,8 +1001,6 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 	struct intel_tv *intel_tv = enc_to_tv(encoder);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
 	u32 tv_ctl;
-	u32 hctl1, hctl2, hctl3;
-	u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
 	u32 scctl1, scctl2, scctl3;
 	int i, j;
 	const struct video_levels *video_levels;
@@ -982,44 +1039,6 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 		burst_ena = tv_mode->burst_ena;
 		break;
 	}
-	hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
-		(tv_mode->htotal << TV_HTOTAL_SHIFT);
-
-	hctl2 = (tv_mode->hburst_start << 16) |
-		(tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
-
-	if (burst_ena)
-		hctl2 |= TV_BURST_ENA;
-
-	hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
-		(tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
-
-	vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
-		(tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
-		(tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
-
-	vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
-		(tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
-		(tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
-
-	vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
-		(tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
-		(tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
-
-	if (tv_mode->veq_ena)
-		vctl3 |= TV_EQUAL_ENA;
-
-	vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
-		(tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
-
-	vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
-		(tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
-
-	vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
-		(tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
-
-	vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
-		(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
 
 	if (intel_crtc->pipe == 1)
 		tv_ctl |= TV_ENC_PIPEB_SELECT;
@@ -1054,16 +1073,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 	if (dev->pdev->device < 0x2772)
 		tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
 
-	I915_WRITE(TV_H_CTL_1, hctl1);
-	I915_WRITE(TV_H_CTL_2, hctl2);
-	I915_WRITE(TV_H_CTL_3, hctl3);
-	I915_WRITE(TV_V_CTL_1, vctl1);
-	I915_WRITE(TV_V_CTL_2, vctl2);
-	I915_WRITE(TV_V_CTL_3, vctl3);
-	I915_WRITE(TV_V_CTL_4, vctl4);
-	I915_WRITE(TV_V_CTL_5, vctl5);
-	I915_WRITE(TV_V_CTL_6, vctl6);
-	I915_WRITE(TV_V_CTL_7, vctl7);
+	set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
+
 	I915_WRITE(TV_SC_CTL_1, scctl1);
 	I915_WRITE(TV_SC_CTL_2, scctl2);
 	I915_WRITE(TV_SC_CTL_3, scctl3);
-- 
1.8.1.4

[PATCH 04/66] drm/i915/tv: extract set_color_conversion

[Daniel Vetter]

intel_tv_mode_set is still too bug.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_tv.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 04bf8caaac0c..a6acaeec7d69 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -993,6 +993,26 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
 	I915_WRITE(TV_V_CTL_7, vctl7);
 }
 
+static void set_color_conversion(struct drm_i915_private *dev_priv,
+				 const struct color_conversion *color_conversion)
+{
+	if (!color_conversion)
+		return;
+
+	I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
+		   color_conversion->gy);
+	I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
+		   color_conversion->ay);
+	I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
+		   color_conversion->gu);
+	I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
+		   color_conversion->au);
+	I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
+		   color_conversion->gv);
+	I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
+		   color_conversion->av);
+}
+
 static void intel_tv_mode_set(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
@@ -1079,20 +1099,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 	I915_WRITE(TV_SC_CTL_2, scctl2);
 	I915_WRITE(TV_SC_CTL_3, scctl3);
 
-	if (color_conversion) {
-		I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
-			   color_conversion->gy);
-		I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
-			   color_conversion->ay);
-		I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
-			   color_conversion->gu);
-		I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
-			   color_conversion->au);
-		I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
-			   color_conversion->gv);
-		I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
-			   color_conversion->av);
-	}
+	set_color_conversion(dev_priv, color_conversion);
 
 	if (INTEL_INFO(dev)->gen >= 4)
 		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
-- 
1.8.1.4

[PATCH 05/66] drm/i915/tv: De-magic device check

[Daniel Vetter]

We only support TV-out on gen3/4 mobile platforms, and i915gm is the
only one that matches.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_tv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index a6acaeec7d69..3fd1ab376883 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1090,7 +1090,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 		tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
 
 	/* Enable two fixes for the chips that need them. */
-	if (dev->pdev->device < 0x2772)
+	if (IS_I915GM(dev))
 		tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
 
 	set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
-- 
1.8.1.4

[PATCH 06/66] drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set

[Daniel Vetter]

The pipe and plane _are_ disabled when we call this. So replace it
all with the corresponding assert (as self-documenting code) and
rip out all the lore.

Checking for a disabled plane would require us to export those macros
from intel_display.c, but if the pipe is off the plane isn't working
either. So this single check is good enough.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_tv.c | 62 ++++++++++++++---------------------------
 1 file changed, 21 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 3fd1ab376883..722fcb709f4d 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1026,7 +1026,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 	const struct video_levels *video_levels;
 	const struct color_conversion *color_conversion;
 	bool burst_ena;
-	int pipe = intel_crtc->pipe;
+	int xpos = 0x0, ypos = 0x0;
+	unsigned int xsize, ysize;
 
 	if (!tv_mode)
 		return;	/* can't happen (mode_prepare prevents this) */
@@ -1110,46 +1111,25 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
 		I915_WRITE(TV_CLR_LEVEL,
 			   ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
 			    (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
-	{
-		int pipeconf_reg = PIPECONF(pipe);
-		int dspcntr_reg = DSPCNTR(intel_crtc->plane);
-		int pipeconf = I915_READ(pipeconf_reg);
-		int dspcntr = I915_READ(dspcntr_reg);
-		int xpos = 0x0, ypos = 0x0;
-		unsigned int xsize, ysize;
-		/* Pipe must be off here */
-		I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
-		intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-
-		/* Wait for vblank for the disable to take effect */
-		if (IS_GEN2(dev))
-			intel_wait_for_vblank(dev, intel_crtc->pipe);
-
-		I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
-		/* Wait for vblank for the disable to take effect. */
-		intel_wait_for_pipe_off(dev, intel_crtc->pipe);
-
-		/* Filter ctl must be set before TV_WIN_SIZE */
-		I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
-		xsize = tv_mode->hblank_start - tv_mode->hblank_end;
-		if (tv_mode->progressive)
-			ysize = tv_mode->nbr_end + 1;
-		else
-			ysize = 2*tv_mode->nbr_end + 1;
-
-		xpos += intel_tv->margin[TV_MARGIN_LEFT];
-		ypos += intel_tv->margin[TV_MARGIN_TOP];
-		xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
-			  intel_tv->margin[TV_MARGIN_RIGHT]);
-		ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
-			  intel_tv->margin[TV_MARGIN_BOTTOM]);
-		I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
-		I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
-
-		I915_WRITE(pipeconf_reg, pipeconf);
-		I915_WRITE(dspcntr_reg, dspcntr);
-		intel_flush_primary_plane(dev_priv, intel_crtc->plane);
-	}
+
+	assert_pipe_disabled(dev_priv, intel_crtc->pipe);
+
+	/* Filter ctl must be set before TV_WIN_SIZE */
+	I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
+	xsize = tv_mode->hblank_start - tv_mode->hblank_end;
+	if (tv_mode->progressive)
+		ysize = tv_mode->nbr_end + 1;
+	else
+		ysize = 2*tv_mode->nbr_end + 1;
+
+	xpos += intel_tv->margin[TV_MARGIN_LEFT];
+	ypos += intel_tv->margin[TV_MARGIN_TOP];
+	xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
+		  intel_tv->margin[TV_MARGIN_RIGHT]);
+	ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
+		  intel_tv->margin[TV_MARGIN_BOTTOM]);
+	I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
+	I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
 
 	j = 0;
 	for (i = 0; i < 60; i++)
-- 
1.8.1.4

[PATCH 07/66] drm/i915/tv: Remove ->mode_set callback

[Daniel Vetter]

Currently for the i9xx crtc hooks there's nothing between the call to
encoder->mode_set and encoder->pre_enable which touches the hardware.

Therefore, since tv is only used on gen3/4, we can just move the hook.
Yay for easy cases!

The only other important thing to check is that the new
->pre_enable hook is idempotent wrt the sw state since now it can
be called multiple times (due to DPMS). After a the bit of refactoring
this is now easy to check: It only reads crtc->config and computes
derived state but otherwise leaves it as-is, so we're good.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_tv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 722fcb709f4d..e0193e8020b8 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1013,7 +1013,7 @@ static void set_color_conversion(struct drm_i915_private *dev_priv,
 		   color_conversion->av);
 }
 
-static void intel_tv_mode_set(struct intel_encoder *encoder)
+static void intel_tv_pre_enable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1632,7 +1632,7 @@ intel_tv_init(struct drm_device *dev)
 
 	intel_encoder->compute_config = intel_tv_compute_config;
 	intel_encoder->get_config = intel_tv_get_config;
-	intel_encoder->mode_set = intel_tv_mode_set;
+	intel_encoder->pre_enable = intel_tv_pre_enable;
 	intel_encoder->enable = intel_enable_tv;
 	intel_encoder->disable = intel_disable_tv;
 	intel_encoder->get_hw_state = intel_tv_get_hw_state;
-- 
1.8.1.4

[PATCH 08/66] drm/i915/crt: Remove ->mode_set callback

[Daniel Vetter]

We only set a few bits in the ADPA register, which we then read back
in the enable/disable hooks. So we can just move that bit of state
computation code to the place where we need it since setting these
bits without enabling the CRT encoder has no effects.

The only exceptions are the hotplug bits since they affect the hotplug
detection logic, but we already set those in the ->reset function and
then never touch them.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c | 76 ++++++++++++++++------------------------
 1 file changed, 30 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index aa5a3dc43342..22d8347f7838 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -144,28 +144,49 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-	u32 temp;
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
+	u32 adpa;
+
+	if (INTEL_INFO(dev)->gen >= 5)
+		adpa = ADPA_HOTPLUG_BITS;
+	else
+		adpa = 0;
 
-	temp = I915_READ(crt->adpa_reg);
-	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
-	temp &= ~ADPA_DAC_ENABLE;
+	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
+	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
+
+	/* For CPT allow 3 pipe config, for others just use A or B */
+	if (HAS_PCH_LPT(dev))
+		; /* Those bits don't exist here */
+	else if (HAS_PCH_CPT(dev))
+		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
+	else if (crtc->pipe == 0)
+		adpa |= ADPA_PIPE_A_SELECT;
+	else
+		adpa |= ADPA_PIPE_B_SELECT;
+
+	if (!HAS_PCH_SPLIT(dev))
+		I915_WRITE(BCLRPAT(crtc->pipe), 0);
 
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
-		temp |= ADPA_DAC_ENABLE;
+		adpa |= ADPA_DAC_ENABLE;
 		break;
 	case DRM_MODE_DPMS_STANDBY:
-		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
+		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 		break;
 	case DRM_MODE_DPMS_SUSPEND:
-		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
+		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 		break;
 	case DRM_MODE_DPMS_OFF:
-		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
+		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 		break;
 	}
 
-	I915_WRITE(crt->adpa_reg, temp);
+	I915_WRITE(crt->adpa_reg, adpa);
 }
 
 static void intel_disable_crt(struct intel_encoder *encoder)
@@ -274,42 +295,6 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
-static void intel_crt_mode_set(struct intel_encoder *encoder)
-{
-
-	struct drm_device *dev = encoder->base.dev;
-	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
-	u32 adpa;
-
-	if (INTEL_INFO(dev)->gen >= 5)
-		adpa = ADPA_HOTPLUG_BITS;
-	else
-		adpa = 0;
-
-	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
-		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
-		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
-
-	/* For CPT allow 3 pipe config, for others just use A or B */
-	if (HAS_PCH_LPT(dev))
-		; /* Those bits don't exist here */
-	else if (HAS_PCH_CPT(dev))
-		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
-	else if (crtc->pipe == 0)
-		adpa |= ADPA_PIPE_A_SELECT;
-	else
-		adpa |= ADPA_PIPE_B_SELECT;
-
-	if (!HAS_PCH_SPLIT(dev))
-		I915_WRITE(BCLRPAT(crtc->pipe), 0);
-
-	I915_WRITE(crt->adpa_reg, adpa);
-}
-
 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
@@ -867,7 +852,6 @@ void intel_crt_init(struct drm_device *dev)
 		crt->adpa_reg = ADPA;
 
 	crt->base.compute_config = intel_crt_compute_config;
-	crt->base.mode_set = intel_crt_mode_set;
 	crt->base.disable = intel_disable_crt;
 	crt->base.enable = intel_enable_crt;
 	if (I915_HAS_HOTPLUG(dev))
-- 
1.8.1.4

[PATCH 09/66] drm/i915/sdvo: Remove ->mode_set callback

[Daniel Vetter]

SDVO is used by both crtcs using the i9xx_ and the ironlake_
functions. For both cases there is nothing between the
encoder->mode_set and the encoder->pre_enable calls that touches the
hardware.

The vlv_ functions are different since they enable the pll before the
->pre_enable hook. But SDVO isn't supported on vlv platforms, so this
doesn't matter.

We've also already clean up all the sdvo state computation logic, all
relevant parts are already in the ->compute_config hook.  So we can
just get rid of the ->mode_set hook by converting it to a ->pre_enable
hook.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 46be00d66df3..2bf09e8eb5ed 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1174,7 +1174,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
-static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
+static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
 {
 	struct drm_device *dev = intel_encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2999,7 +2999,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
 
 	intel_encoder->compute_config = intel_sdvo_compute_config;
 	intel_encoder->disable = intel_disable_sdvo;
-	intel_encoder->mode_set = intel_sdvo_mode_set;
+	intel_encoder->pre_enable = intel_sdvo_pre_enable;
 	intel_encoder->enable = intel_enable_sdvo;
 	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
 	intel_encoder->get_config = intel_sdvo_get_config;
-- 
1.8.1.4

[PATCH 10/66] drm/i915/hdmi: Enable hdmi mode on g4x, too

[Daniel Vetter]

For compliance we really should be sending NULL infoframes always
when we detect a hdmi capable monitor. Also remove the now redudant
setting for the has_audio case and enforce that audio is only
possible with a hdmi sink.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b606162cc17c..fcee1702774c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -650,15 +650,14 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 	else
 		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 
-	if (intel_hdmi->has_hdmi_sink &&
-	    (HAS_PCH_CPT(dev) || IS_VALLEYVIEW(dev)))
+	if (intel_hdmi->has_hdmi_sink)
 		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 
 	if (intel_hdmi->has_audio) {
+		WARN_ON(!intel_hdmi->has_hdmi_sink);
 		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 				 pipe_name(crtc->pipe));
 		hdmi_val |= SDVO_AUDIO_ENABLE;
-		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 		intel_write_eld(&encoder->base, adjusted_mode);
 	}
 
-- 
1.8.1.4

[PATCH 11/66] drm/i915: Track hdmi mode in the pipe config

[Daniel Vetter]

Also add state readout and cross-check support. The only invasive change
is wiring up the new flag to the ->set_infoframes callbacks.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c     |  9 +++++----
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_drv.h     |  4 ++++
 drivers/gpu/drm/i915/intel_hdmi.c    | 36 +++++++++++++++++++++++++-----------
 4 files changed, 35 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e9600063..94dc62607a1a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -409,7 +409,9 @@ static void intel_ddi_mode_set(struct intel_encoder *encoder)
 			intel_write_eld(&encoder->base, adjusted_mode);
 		}
 
-		intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
+		intel_hdmi->set_infoframes(&encoder->base,
+					   crtc->config.has_hdmi_sink,
+					   adjusted_mode);
 	}
 }
 
@@ -1062,9 +1064,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 	}
 
 	if (type == INTEL_OUTPUT_HDMI) {
-		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-
-		if (intel_hdmi->has_hdmi_sink)
+		if (intel_crtc->config.has_hdmi_sink)
 			temp |= TRANS_DDI_MODE_SELECT_HDMI;
 		else
 			temp |= TRANS_DDI_MODE_SELECT_DVI;
@@ -1580,6 +1580,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
 	case TRANS_DDI_MODE_SELECT_HDMI:
+		pipe_config->has_hdmi_sink = true;
 	case TRANS_DDI_MODE_SELECT_DVI:
 	case TRANS_DDI_MODE_SELECT_FDI:
 		break;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5fed7aaf879d..01485c4ff1ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9615,6 +9615,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
+	PIPE_CONF_CHECK_I(has_hdmi_sink);
 
 	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b885df150910..d8cafb7e85ec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -273,6 +273,9 @@ struct intel_crtc_config {
 	 * accordingly. */
 	bool has_dp_encoder;
 
+	/* Whether we should send NULL infoframes. Required for audio. */
+	bool has_hdmi_sink;
+
 	/*
 	 * Enable dithering, used when the selected pipe bpp doesn't match the
 	 * plane bpp.
@@ -484,6 +487,7 @@ struct intel_hdmi {
 				enum hdmi_infoframe_type type,
 				const void *frame, ssize_t len);
 	void (*set_infoframes)(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode);
 };
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fcee1702774c..608292d5c428 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -418,6 +418,7 @@ intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 }
 
 static void g4x_set_infoframes(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -440,7 +441,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
 	 * either. */
 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
-	if (!intel_hdmi->has_hdmi_sink) {
+	if (!enable) {
 		if (!(val & VIDEO_DIP_ENABLE))
 			return;
 		val &= ~VIDEO_DIP_ENABLE;
@@ -471,6 +472,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
 }
 
 static void ibx_set_infoframes(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -486,7 +488,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
 	/* See the big comment in g4x_set_infoframes() */
 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
-	if (!intel_hdmi->has_hdmi_sink) {
+	if (!enable) {
 		if (!(val & VIDEO_DIP_ENABLE))
 			return;
 		val &= ~VIDEO_DIP_ENABLE;
@@ -518,6 +520,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
 }
 
 static void cpt_set_infoframes(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -531,7 +534,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
 	/* See the big comment in g4x_set_infoframes() */
 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
-	if (!intel_hdmi->has_hdmi_sink) {
+	if (!enable) {
 		if (!(val & VIDEO_DIP_ENABLE))
 			return;
 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
@@ -554,6 +557,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
 }
 
 static void vlv_set_infoframes(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -569,7 +573,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
 	/* See the big comment in g4x_set_infoframes() */
 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
-	if (!intel_hdmi->has_hdmi_sink) {
+	if (!enable) {
 		if (!(val & VIDEO_DIP_ENABLE))
 			return;
 		val &= ~VIDEO_DIP_ENABLE;
@@ -601,6 +605,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
 }
 
 static void hsw_set_infoframes(struct drm_encoder *encoder,
+			       bool enable,
 			       struct drm_display_mode *adjusted_mode)
 {
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -611,7 +616,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
 
 	assert_hdmi_port_disabled(intel_hdmi);
 
-	if (!intel_hdmi->has_hdmi_sink) {
+	if (!enable) {
 		I915_WRITE(reg, 0);
 		POSTING_READ(reg);
 		return;
@@ -650,11 +655,11 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 	else
 		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 
-	if (intel_hdmi->has_hdmi_sink)
+	if (crtc->config.has_hdmi_sink)
 		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 
 	if (intel_hdmi->has_audio) {
-		WARN_ON(!intel_hdmi->has_hdmi_sink);
+		WARN_ON(!crtc->config.has_hdmi_sink);
 		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 				 pipe_name(crtc->pipe));
 		hdmi_val |= SDVO_AUDIO_ENABLE;
@@ -716,6 +721,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 	else
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
+	if (tmp & HDMI_MODE_SELECT_HDMI)
+		pipe_config->has_hdmi_sink = true;
+
 	pipe_config->adjusted_mode.flags |= flags;
 
 	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
@@ -892,9 +900,11 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 	int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 	int desired_bpp;
 
+	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
+
 	if (intel_hdmi->color_range_auto) {
 		/* See CEA-861-E - 5.1 Default Encoding Parameters */
-		if (intel_hdmi->has_hdmi_sink &&
+		if (pipe_config->has_hdmi_sink &&
 		    drm_match_cea_mode(adjusted_mode) > 1)
 			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 		else
@@ -913,7 +923,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 	 * outputs. We also need to check that the higher clock still fits
 	 * within limits.
 	 */
-	if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
+	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
 	    clock_12bpc <= portclock_limit &&
 	    hdmi_12bpc_possible(encoder->new_crtc)) {
 		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
@@ -1120,7 +1130,9 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
 
-	intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
+	intel_hdmi->set_infoframes(&encoder->base,
+				   intel_crtc->config.has_hdmi_sink,
+				   adjusted_mode);
 }
 
 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
@@ -1166,7 +1178,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
 	mutex_unlock(&dev_priv->dpio_lock);
 
-	intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
+	intel_hdmi->set_infoframes(&encoder->base,
+				   intel_crtc->config.has_hdmi_sink,
+				   adjusted_mode);
 
 	intel_enable_hdmi(encoder);
 
-- 
1.8.1.4

[PATCH 12/66] drm/i915/sdvo: Use pipe_config->limited_color_range consistently

[Daniel Vetter]

We in the pre_enable hook we should only rely on the pipe config and
not on some other state set through properties or detect functions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 2bf09e8eb5ed..e43bf558f0cd 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1159,14 +1159,13 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
 		 * bit per color mode. */
 		if (intel_sdvo->has_hdmi_monitor &&
 		    drm_match_cea_mode(adjusted_mode) > 1)
-			intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
-		else
-			intel_sdvo->color_range = 0;
+			pipe_config->limited_color_range = true;
+	} else {
+		if (intel_sdvo->has_hdmi_monitor &&
+		    intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
+			pipe_config->limited_color_range = true;
 	}
 
-	if (intel_sdvo->color_range)
-		pipe_config->limited_color_range = true;
-
 	/* Clock computation needs to happen after pixel multiplier. */
 	if (intel_sdvo->is_tv)
 		i9xx_adjust_sdvo_tv_clock(pipe_config);
@@ -1258,8 +1257,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
 		/* The real mode polarity is set by the SDVO commands, using
 		 * struct intel_sdvo_dtd. */
 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
-		if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
-			sdvox |= intel_sdvo->color_range;
+		if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range)
+			sdvox |= HDMI_COLOR_RANGE_16_235;
 		if (INTEL_INFO(dev)->gen < 5)
 			sdvox |= SDVO_BORDER_ENABLE;
 	} else {
-- 
1.8.1.4

[PATCH 13/66] drm/i915: state readout and cross checking for limited_color_range

[Daniel Vetter]

At least on those platforms which have a simple bit and don't rely
on the fully programmable CSC unit to do this.

Note that with the current code this includes CHV, but I guess that
platform will match BYT.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 drivers/gpu/drm/i915/intel_sdvo.c    | 6 +++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01485c4ff1ba..099159e4881c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5791,6 +5791,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 		}
 	}
 
+	if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+		pipe_config->limited_color_range = true;
+
 	if (INTEL_INFO(dev)->gen < 4)
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
@@ -6795,6 +6798,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 		break;
 	}
 
+	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
+		pipe_config->limited_color_range = true;
+
 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
 		struct intel_shared_dpll *pll;
 
@@ -9616,6 +9622,9 @@ intel_pipe_config_compare(struct drm_device *dev,
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(has_hdmi_sink);
+	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
+	    IS_VALLEYVIEW(dev))
+		PIPE_CONF_CHECK_I(limited_color_range);
 
 	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e43bf558f0cd..650525a654a3 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1348,6 +1348,8 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 	u8 val;
 	bool ret;
 
+	sdvox = I915_READ(intel_sdvo->sdvo_reg);
+
 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
 	if (!ret) {
 		/* Some sdvo encoders are not spec compliant and don't
@@ -1376,7 +1378,6 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 	 * other platfroms.
 	 */
 	if (IS_I915G(dev) || IS_I915GM(dev)) {
-		sdvox = I915_READ(intel_sdvo->sdvo_reg);
 		pipe_config->pixel_multiplier =
 			((sdvox & SDVO_PORT_MULTIPLY_MASK)
 			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
@@ -1405,6 +1406,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 		}
 	}
 
+	if (sdvox & HDMI_COLOR_RANGE_16_235)
+		pipe_config->limited_color_range = true;
+
 	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
 	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
 	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
-- 
1.8.1.4

[PATCH 14/66] drm/i915/sdvo: use config->has_hdmi_sink

[Daniel Vetter]

This way we can rely on the state cross-checker to have a bit
assurance that we'll get it right.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 650525a654a3..aa2c609fccf1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1153,15 +1153,17 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
 	pipe_config->pixel_multiplier =
 		intel_sdvo_get_pixel_multiplier(adjusted_mode);
 
+	pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
+
 	if (intel_sdvo->color_range_auto) {
 		/* See CEA-861-E - 5.1 Default Encoding Parameters */
 		/* FIXME: This bit is only valid when using TMDS encoding and 8
 		 * bit per color mode. */
-		if (intel_sdvo->has_hdmi_monitor &&
+		if (pipe_config->has_hdmi_sink &&
 		    drm_match_cea_mode(adjusted_mode) > 1)
 			pipe_config->limited_color_range = true;
 	} else {
-		if (intel_sdvo->has_hdmi_monitor &&
+		if (pipe_config->has_hdmi_sink &&
 		    intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
 			pipe_config->limited_color_range = true;
 	}
@@ -1222,7 +1224,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
 	if (!intel_sdvo_set_target_input(intel_sdvo))
 		return;
 
-	if (intel_sdvo->has_hdmi_monitor) {
+	if (crtc->config.has_hdmi_sink) {
 		intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
 		intel_sdvo_set_colorimetry(intel_sdvo,
 					   SDVO_COLORIMETRY_RGB256);
@@ -1409,6 +1411,12 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 	if (sdvox & HDMI_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
+	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
+				 &val, 1)) {
+		if (val == SDVO_ENCODE_HDMI)
+			pipe_config->has_hdmi_sink = true;
+	}
+
 	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
 	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
 	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
-- 
1.8.1.4

[PATCH 15/66] drm/i915: Simplify audio handling on DDI ports

[Daniel Vetter]

There's no need to check whether audio is enabled (which for ddi ports
is done through the crtc->eld_vld flag) since at the cost of a
potentially unecessary register rmw cycle we can unconditionally do
this.

Note that the edp check is just paranoia since we won't ever call the
write_eld function for an edp panel.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 94dc62607a1a..527fea50e599 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1403,12 +1403,10 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
 
-	if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
-		tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
-		tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
-			 (pipe * 4));
-		I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
-	}
+	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
+	tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
+		 (pipe * 4));
+	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 
 	if (type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-- 
1.8.1.4

[PATCH 16/66] drm/i915: Track has_audio in the pipe config

[Daniel Vetter]

Including state readout and cross-checking. This allows us to get rid
of crtc->eld_vld on hsw+. It also means that fastboot will be unhappy
if the BIOS hasn't set up the audio routing like we want it too.

Wrt fastboot and external screens I see a few options:
- Don't.
- Try to fix up eld, infoframes and audio settings after the fact. But
  that means some pretty extensive reworking of our code which
  currently does all this while the pipe/port is still off.

I won't bother with converting SDVO over to this because the audio
support for SDVO is very lacking:
- We don't update the eld.
- We don't update the audio state on the sdvo encoder.
- We don't check whether the platform can even feed audio to the sdvo
  encoder.

I've converted hdmi, dp & ddi all in one go since ddi needs both hdmi
and dp converted and so doing it step-by-step would have required a
few intermediate hacks.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 38 +++++++++++++-----------------------
 drivers/gpu/drm/i915/intel_display.c |  6 ++----
 drivers/gpu/drm/i915/intel_dp.c      |  8 ++++++--
 drivers/gpu/drm/i915/intel_drv.h     |  5 ++++-
 drivers/gpu/drm/i915/intel_hdmi.c    | 10 ++++++++--
 5 files changed, 34 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 527fea50e599..096a7b94ec2b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -375,7 +375,15 @@ static void intel_ddi_mode_set(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
 		      port_name(port), pipe_name(pipe));
 
-	crtc->eld_vld = false;
+	if (crtc->config.has_audio) {
+		DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
+				 pipe_name(crtc->pipe));
+
+		/* write eld */
+		DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
+		intel_write_eld(&encoder->base, adjusted_mode);
+	}
+
 	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 		struct intel_digital_port *intel_dig_port =
@@ -384,31 +392,9 @@ static void intel_ddi_mode_set(struct intel_encoder *encoder)
 		intel_dp->DP = intel_dig_port->saved_port_bits |
 			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 		intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
-
-		if (intel_dp->has_audio) {
-			DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
-					 pipe_name(crtc->pipe));
-
-			/* write eld */
-			DRM_DEBUG_DRIVER("DP audio: write eld information\n");
-			intel_write_eld(&encoder->base, adjusted_mode);
-		}
 	} else if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 
-		if (intel_hdmi->has_audio) {
-			/* Proper support for digital audio needs a new logic
-			 * and a new set of registers, so we leave it for future
-			 * patch bombing.
-			 */
-			DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
-					 pipe_name(crtc->pipe));
-
-			/* write eld */
-			DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
-			intel_write_eld(&encoder->base, adjusted_mode);
-		}
-
 		intel_hdmi->set_infoframes(&encoder->base,
 					   crtc->config.has_hdmi_sink,
 					   adjusted_mode);
@@ -1385,7 +1371,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
 		intel_edp_psr_enable(intel_dp);
 	}
 
-	if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
+	if (intel_crtc->config.has_audio) {
 		tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 		tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
 		I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
@@ -1591,6 +1577,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		break;
 	}
 
+	temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
+	if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
+		pipe_config->has_audio = true;
+
 	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
 		/*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 099159e4881c..f8ebe9b59746 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4532,13 +4532,11 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct drm_connector *connector;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
 	/* crtc should still be enabled when we disable it. */
 	WARN_ON(!crtc->enabled);
 
 	dev_priv->display.crtc_disable(crtc);
-	intel_crtc->eld_vld = false;
 	intel_crtc_update_sarea(crtc, false);
 	dev_priv->display.off(crtc);
 
@@ -7347,7 +7345,6 @@ static void haswell_write_eld(struct drm_connector *connector,
 {
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 	uint8_t *eld = connector->eld;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t eldv;
 	uint32_t i;
 	int len;
@@ -7386,7 +7383,6 @@ static void haswell_write_eld(struct drm_connector *connector,
 	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 
 	eldv = AUDIO_ELD_VALID_A << (pipe * 4);
-	intel_crtc->eld_vld = true;
 
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
@@ -9626,6 +9622,8 @@ intel_pipe_config_compare(struct drm_device *dev,
 	    IS_VALLEYVIEW(dev))
 		PIPE_CONF_CHECK_I(limited_color_range);
 
+	PIPE_CONF_CHECK_I(has_audio);
+
 	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a421c81f2d88..fded70572ff2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -775,6 +775,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		pipe_config->has_pch_encoder = true;
 
 	pipe_config->has_dp_encoder = true;
+	pipe_config->has_audio = intel_dp->has_audio;
 
 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
@@ -934,7 +935,7 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 
-	if (intel_dp->has_audio) {
+	if (crtc->config.has_audio) {
 		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 				 pipe_name(crtc->pipe));
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
@@ -1477,8 +1478,11 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	int dotclock;
 
+	tmp = I915_READ(intel_dp->output_reg);
+	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
+		pipe_config->has_audio = true;
+
 	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
-		tmp = I915_READ(intel_dp->output_reg);
 		if (tmp & DP_SYNC_HS_HIGH)
 			flags |= DRM_MODE_FLAG_PHSYNC;
 		else
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d8cafb7e85ec..c85f5e5ddc7c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -276,6 +276,10 @@ struct intel_crtc_config {
 	/* Whether we should send NULL infoframes. Required for audio. */
 	bool has_hdmi_sink;
 
+	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
+	 * has_dp_encoder is set. */
+	bool has_audio;
+
 	/*
 	 * Enable dithering, used when the selected pipe bpp doesn't match the
 	 * plane bpp.
@@ -366,7 +370,6 @@ struct intel_crtc {
 	 */
 	bool active;
 	unsigned long enabled_power_domains;
-	bool eld_vld;
 	bool primary_enabled; /* is the primary plane (partially) visible? */
 	bool lowfreq_avail;
 	struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 608292d5c428..7f18c19b91f9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -658,7 +658,7 @@ static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 	if (crtc->config.has_hdmi_sink)
 		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 
-	if (intel_hdmi->has_audio) {
+	if (crtc->config.has_audio) {
 		WARN_ON(!crtc->config.has_hdmi_sink);
 		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 				 pipe_name(crtc->pipe));
@@ -724,6 +724,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 	if (tmp & HDMI_MODE_SELECT_HDMI)
 		pipe_config->has_hdmi_sink = true;
 
+	if (tmp & HDMI_MODE_SELECT_HDMI)
+		pipe_config->has_audio = true;
+
 	pipe_config->adjusted_mode.flags |= flags;
 
 	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
@@ -746,7 +749,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
 	u32 temp;
 	u32 enable_bits = SDVO_ENABLE;
 
-	if (intel_hdmi->has_audio)
+	if (intel_crtc->config.has_audio)
 		enable_bits |= SDVO_AUDIO_ENABLE;
 
 	temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -917,6 +920,9 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 		pipe_config->has_pch_encoder = true;
 
+	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
+		pipe_config->has_audio = true;
+
 	/*
 	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
-- 
1.8.1.4

[PATCH 17/66] drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp

[Daniel Vetter]

Only ilk/snb/ivb need the port A pll setup, so move it to the
pre_enable hook for those platforms. We can savely do this since on
those platforms there's nothing that touches the hardware between the
encoder->mode_set and the encoder->pre_enable calls.

Also add a comment that port A is ilk+ only.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fded70572ff2..eec1afb72a57 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -973,9 +973,6 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
 	} else {
 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 	}
-
-	if (port == PORT_A && !IS_VALLEYVIEW(dev))
-		ironlake_set_pll_cpu_edp(intel_dp);
 }
 
 #define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
@@ -1876,8 +1873,11 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 
-	if (dport->port == PORT_A)
+	/* Only ilk+ has port A */
+	if (dport->port == PORT_A) {
+		ironlake_set_pll_cpu_edp(intel_dp);
 		ironlake_edp_pll_on(intel_dp);
+	}
 }
 
 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
-- 
1.8.1.4

[PATCH 18/66] drm/i915/dp: Remove ->mode_set callback

[Daniel Vetter]

With all the preceding refactoring the dp mode_set callback only
computes a bit of state (all derived from the pipe config) and also
writes the eld. As long as we do that before we enable the audio bit
or depend upon the correct value in intel_dp->DP we'll be fine.

No other hw state is touched.

We therefore only need to check that clearing intel_dp->DP is save.
Which it is since when we re-enable we already mask out all the bits
the link training code sets. And we need to keep on doing that so that
the re-train loop walking over pre-emph/voltage-swing values still
works properly.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eec1afb72a57..5746fe22dde3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -900,7 +900,7 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 	udelay(500);
 }
 
-static void intel_dp_mode_set(struct intel_encoder *encoder)
+static void intel_dp_prepare(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1873,6 +1873,8 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 
+	intel_dp_prepare(encoder);
+
 	/* Only ilk+ has port A */
 	if (dport->port == PORT_A) {
 		ironlake_set_pll_cpu_edp(intel_dp);
@@ -1929,6 +1931,8 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 
+	intel_dp_prepare(encoder);
+
 	/* Program Tx lane resets to default */
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
@@ -4012,7 +4016,6 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 			 DRM_MODE_ENCODER_TMDS);
 
 	intel_encoder->compute_config = intel_dp_compute_config;
-	intel_encoder->mode_set = intel_dp_mode_set;
 	intel_encoder->disable = intel_disable_dp;
 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
 	intel_encoder->get_config = intel_dp_get_config;
-- 
1.8.1.4

[PATCH 19/66] drm/i915/hdmi: Remove redundant IS_VLV checks

[Daniel Vetter]

Those functions are only used on vlv platforms, so no need to check.
Especially if we're not too consistent about it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 7f18c19b91f9..1a3e5ba9c547 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1155,9 +1155,6 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
 	int pipe = intel_crtc->pipe;
 	u32 val;
 
-	if (!IS_VALLEYVIEW(dev))
-		return;
-
 	/* Enable clock channels for this port */
 	mutex_lock(&dev_priv->dpio_lock);
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
@@ -1203,9 +1200,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 
-	if (!IS_VALLEYVIEW(dev))
-		return;
-
 	/* Program Tx lane resets to default */
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
-- 
1.8.1.4

[PATCH 20/66] drm/i915/hdmi: Remove ->mode_set callback

[Daniel Vetter]

Similar to dp the only thing we do is call intel_write_eld and prepare
a bit of state for the enable hooks. The only difference is that we
write that to the hardware instead of keeping track of it somewhere in
software.

Still we can just move all this to the very first enable hook.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1a3e5ba9c547..ced93bd33f80 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -633,7 +633,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
 	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 }
 
-static void intel_hdmi_mode_set(struct intel_encoder *encoder)
+static void intel_hdmi_prepare(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1136,6 +1136,8 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
 
+	intel_hdmi_prepare(encoder);
+
 	intel_hdmi->set_infoframes(&encoder->base,
 				   intel_crtc->config.has_hdmi_sink,
 				   adjusted_mode);
@@ -1200,6 +1202,8 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 
+	intel_hdmi_prepare(encoder);
+
 	/* Program Tx lane resets to default */
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
@@ -1367,7 +1371,6 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 			 DRM_MODE_ENCODER_TMDS);
 
 	intel_encoder->compute_config = intel_hdmi_compute_config;
-	intel_encoder->mode_set = intel_hdmi_mode_set;
 	intel_encoder->disable = intel_disable_hdmi;
 	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 	intel_encoder->get_config = intel_hdmi_get_config;
-- 
1.8.1.4

[PATCH 21/66] drm/i915/lvds: Remove ->mode_set callback

[Daniel Vetter]

All the hard work was already done, only thing left to do is remove
the empty callback. And a now rather misleading comment I've spotted
while reading through code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_lvds.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 1b1541dfb440..d1539f3efe44 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -119,10 +119,6 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 	pipe_config->adjusted_mode.crtc_clock = dotclock;
 }
 
-/* The LVDS pin pair needs to be on before the DPLLs are enabled.
- * This is an exception to the general rule that mode_set doesn't turn
- * things on.
- */
 static void intel_pre_enable_lvds(struct intel_encoder *encoder)
 {
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
@@ -324,15 +320,6 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	return true;
 }
 
-static void intel_lvds_mode_set(struct intel_encoder *encoder)
-{
-	/*
-	 * We don't do anything here, the LVDS port is fully set up in the pre
-	 * enable hook - the ordering constraints for enabling the lvds port vs.
-	 * enabling the display pll are too strict.
-	 */
-}
-
 /**
  * Detect the LVDS connection.
  *
@@ -946,7 +933,6 @@ void intel_lvds_init(struct drm_device *dev)
 	intel_encoder->enable = intel_enable_lvds;
 	intel_encoder->pre_enable = intel_pre_enable_lvds;
 	intel_encoder->compute_config = intel_lvds_compute_config;
-	intel_encoder->mode_set = intel_lvds_mode_set;
 	intel_encoder->disable = intel_disable_lvds;
 	intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 	intel_encoder->get_config = intel_lvds_get_config;
-- 
1.8.1.4

[PATCH 22/66] drm/i915/ddi: Remove ->mode_set callback

[Daniel Vetter]

A bit more care required here since there are some very few things
between the call to encoder->mode_set and encoder->pre_enable. But
they're either book-keeping or only matter for the vga port on the
pch. So of no concern.

Note that with the new sequence we write the infoframes after
selecting the clock source, but that shouldn't matter. I've simply
opted for this to have simpler code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c | 66 +++++++++++++++-------------------------
 1 file changed, 24 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 096a7b94ec2b..271ce19ee880 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -364,43 +364,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 	DRM_ERROR("FDI link training failed!\n");
 }
 
-static void intel_ddi_mode_set(struct intel_encoder *encoder)
-{
-	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-	int port = intel_ddi_get_encoder_port(encoder);
-	int pipe = crtc->pipe;
-	int type = encoder->type;
-	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
-
-	DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
-		      port_name(port), pipe_name(pipe));
-
-	if (crtc->config.has_audio) {
-		DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
-				 pipe_name(crtc->pipe));
-
-		/* write eld */
-		DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
-		intel_write_eld(&encoder->base, adjusted_mode);
-	}
-
-	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-		struct intel_digital_port *intel_dig_port =
-			enc_to_dig_port(&encoder->base);
-
-		intel_dp->DP = intel_dig_port->saved_port_bits |
-			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
-		intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
-	} else if (type == INTEL_OUTPUT_HDMI) {
-		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-
-		intel_hdmi->set_infoframes(&encoder->base,
-					   crtc->config.has_hdmi_sink,
-					   adjusted_mode);
-	}
-}
-
 static struct intel_encoder *
 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 {
@@ -1279,28 +1242,48 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
-	struct drm_crtc *crtc = encoder->crtc;
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 	int type = intel_encoder->type;
 
+	if (crtc->config.has_audio) {
+		DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
+				 pipe_name(crtc->pipe));
+
+		/* write eld */
+		DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
+		intel_write_eld(encoder, &crtc->config.adjusted_mode);
+	}
+
 	if (type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 		intel_edp_panel_on(intel_dp);
 	}
 
-	WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
-	I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
+	WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
+	I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
 
 	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		struct intel_digital_port *intel_dig_port =
+			enc_to_dig_port(encoder);
+
+		intel_dp->DP = intel_dig_port->saved_port_bits |
+			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
+		intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 		intel_dp_start_link_train(intel_dp);
 		intel_dp_complete_link_train(intel_dp);
 		if (port != PORT_A)
 			intel_dp_stop_link_train(intel_dp);
+	} else if (type == INTEL_OUTPUT_HDMI) {
+		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+
+		intel_hdmi->set_infoframes(encoder,
+					   crtc->config.has_hdmi_sink,
+					   &crtc->config.adjusted_mode);
 	}
 }
 
@@ -1697,7 +1680,6 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 			 DRM_MODE_ENCODER_TMDS);
 
 	intel_encoder->compute_config = intel_ddi_compute_config;
-	intel_encoder->mode_set = intel_ddi_mode_set;
 	intel_encoder->enable = intel_enable_ddi;
 	intel_encoder->pre_enable = intel_ddi_pre_enable;
 	intel_encoder->disable = intel_disable_ddi;
-- 
1.8.1.4

[PATCH 23/66] drm/i915/dsi: Remove ->mode_set callback

[Daniel Vetter]

Looking at our current dsi driver I note that:
- We don't have any slave driver right now.
- There's zero support for the hardware state readout and cross check
  code.
- All the modeset state seems to be tracked in the intel_dsi structure
  instead of the pipe config.

Given all that I can't properly audit the dsi ->mode_set callback. So
just do it as the first thing in the ->pre_pll_enable hook and hope
for the best.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_dsi.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e271c768fd0..7723f6b8fdd1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -94,13 +94,6 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
-static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
-{
-	DRM_DEBUG_KMS("\n");
-
-	vlv_enable_dsi_pll(encoder);
-}
-
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -428,7 +421,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 }
 
-static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
+static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_device *dev = encoder->dev;
@@ -562,6 +555,15 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 				RANDOM_DPI_DISPLAY_RESOLUTION);
 }
 
+static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
+{
+	DRM_DEBUG_KMS("\n");
+
+	intel_dsi_prepare(encoder);
+
+	vlv_enable_dsi_pll(encoder);
+}
+
 static enum drm_connector_status
 intel_dsi_detect(struct drm_connector *connector, bool force)
 {
@@ -668,7 +670,6 @@ bool intel_dsi_init(struct drm_device *dev)
 	intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 	intel_encoder->pre_enable = intel_dsi_pre_enable;
 	intel_encoder->enable = intel_dsi_enable_nop;
-	intel_encoder->mode_set = intel_dsi_mode_set;
 	intel_encoder->disable = intel_dsi_disable;
 	intel_encoder->post_disable = intel_dsi_post_disable;
 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
-- 
1.8.1.4

[PATCH 24/66] drm/i915: Stop calling encoder->mode_set

[Daniel Vetter]

All the callbacks are gone now.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 33 ++-------------------------------
 1 file changed, 2 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f8ebe9b59746..dec4127a4738 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7202,35 +7202,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	return true;
 }
 
-static int intel_crtc_mode_set(struct drm_crtc *crtc,
-			       int x, int y,
-			       struct drm_framebuffer *fb)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_encoder *encoder;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
-	int ret;
-
-	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
-
-	if (ret != 0)
-		return ret;
-
-	for_each_encoder_on_crtc(dev, crtc, encoder) {
-		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
-			encoder->base.base.id,
-			drm_get_encoder_name(&encoder->base),
-			mode->base.id, mode->name);
-
-		if (encoder->mode_set)
-			encoder->mode_set(encoder);
-	}
-
-	return 0;
-}
-
 static struct {
 	int clock;
 	u32 config;
@@ -9994,8 +9965,8 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * on the DPLL.
 	 */
 	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
-		ret = intel_crtc_mode_set(&intel_crtc->base,
-					  x, y, fb);
+		ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
+						      x, y, fb);
 		if (ret)
 			goto done;
 	}
-- 
1.8.1.4

[PATCH 25/66] drm/i915: Make ->update_primary_plane infallible

[Daniel Vetter]

Way back we've used this to reject framebuffers with unsupported
pixel formats. But since the modesetting reorg with the compute
config stage we reject those much earlier and just BUG() in this
callback. So switch to a void return type.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  6 +++---
 drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++-------------------
 2 files changed, 13 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d6acb401fd9..e6c16068010f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -463,9 +463,9 @@ struct drm_i915_display_funcs {
 			  struct drm_framebuffer *fb,
 			  struct drm_i915_gem_object *obj,
 			  uint32_t flags);
-	int (*update_primary_plane)(struct drm_crtc *crtc,
-				    struct drm_framebuffer *fb,
-				    int x, int y);
+	void (*update_primary_plane)(struct drm_crtc *crtc,
+				     struct drm_framebuffer *fb,
+				     int x, int y);
 	void (*hpd_irq_setup)(struct drm_device *dev);
 	/* clock updates for mode set */
 	/* cursor updates */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dec4127a4738..b3bd25109ea3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2142,9 +2142,9 @@ static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
 	}
 }
 
-static int i9xx_update_primary_plane(struct drm_crtc *crtc,
-				     struct drm_framebuffer *fb,
-				     int x, int y)
+static void i9xx_update_primary_plane(struct drm_crtc *crtc,
+				      struct drm_framebuffer *fb,
+				      int x, int y)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2230,13 +2230,11 @@ static int i9xx_update_primary_plane(struct drm_crtc *crtc,
 	} else
 		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
 	POSTING_READ(reg);
-
-	return 0;
 }
 
-static int ironlake_update_primary_plane(struct drm_crtc *crtc,
-					 struct drm_framebuffer *fb,
-					 int x, int y)
+static void ironlake_update_primary_plane(struct drm_crtc *crtc,
+					  struct drm_framebuffer *fb,
+					  int x, int y)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2314,8 +2312,6 @@ static int ironlake_update_primary_plane(struct drm_crtc *crtc,
 		I915_WRITE(DSPLINOFF(plane), linear_offset);
 	}
 	POSTING_READ(reg);
-
-	return 0;
 }
 
 /* Assume fb object is pinned & idle & fenced and just update base pointers */
@@ -2330,7 +2326,9 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 		dev_priv->display.disable_fbc(dev);
 	intel_increase_pllclock(crtc);
 
-	return dev_priv->display.update_primary_plane(crtc, fb, x, y);
+	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+
+	return 0;
 }
 
 void intel_display_handle_reset(struct drm_device *dev)
@@ -2489,14 +2487,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 		intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
 	}
 
-	ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
-	if (ret) {
-		mutex_lock(&dev->struct_mutex);
-		intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
-		mutex_unlock(&dev->struct_mutex);
-		DRM_ERROR("failed to update base address\n");
-		return ret;
-	}
+	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
 	old_fb = crtc->primary->fb;
 	crtc->primary->fb = fb;
-- 
1.8.1.4

[PATCH 26/66] drm/i915: More cargo-culted locking for intel_update_fbc

[Daniel Vetter]

Just for consistency, this patch won't fix anything really.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b3bd25109ea3..2f46658d6d53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4344,7 +4344,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	intel_enable_planes(crtc);
 	intel_crtc_update_cursor(crtc, true);
 
+	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	mutex_unlock(&dev->struct_mutex);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->enable(encoder);
@@ -4393,7 +4395,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	/* Give the overlay scaler a chance to enable if it's on this pipe */
 	intel_crtc_dpms_overlay(intel_crtc, true);
 
+	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	mutex_unlock(&dev->struct_mutex);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		encoder->enable(encoder);
@@ -4460,7 +4464,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	intel_crtc->active = false;
 	intel_update_watermarks(crtc);
 
+	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	mutex_unlock(&dev->struct_mutex);
 }
 
 static void i9xx_crtc_off(struct drm_crtc *crtc)
-- 
1.8.1.4

[PATCH 27/66] drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable

[Daniel Vetter]

My plan here is to split up set_base into a prepare step, which does
the pinning, and a commit stage, which updates the hw state. Eventually
we should be able to move the prepare step at the beginning of any
atomic update. For now I only want to move the commit step into the
crtc_enable callbacks.

As a prep step sprinkle intel_edp_psr_update all over the place so
that we don't have to concern ourselves with that in the commit step.

v2: Rebase on top of Ville's enable/disable functions for all planes.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f46658d6d53..202b33817902 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3643,6 +3643,7 @@ static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 
 	drm_vblank_on(dev, pipe);
@@ -3902,6 +3903,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -3949,6 +3951,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 }
 
@@ -4346,6 +4349,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4397,6 +4401,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4466,6 +4471,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
+	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
 }
 
-- 
1.8.1.4

[PATCH 28/66] drm/i915: Inline set_base into crtc_mode_set

[Daniel Vetter]

A lot of the code in set_base is uncessary when the crtc is off, so we
can get rid of it all. Also, we don't need to call the fbc/psr update
functions since the crtc enable/disable hooks do that already.

The only things we really need are:
- Pin the new framebuffer and potentially unpin the old framebuffer
  (if the crtc has been on and we only change the configuration).
- Update the plane registers.

The first step will move out of platform code with the very next
patch.

v2: Don't forget about haswell ...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 69 ++++++++++++++++++++++++++++++++----
 1 file changed, 63 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 202b33817902..a847cee2a336 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5538,6 +5538,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	bool is_lvds = false, is_dsi = false;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
+	struct drm_framebuffer *old_fb;
 	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -5636,9 +5637,27 @@ skip_dpll:
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
 
-	ret = intel_pipe_set_base(crtc, x, y, fb);
+	mutex_lock(&dev->struct_mutex);
+	ret = intel_pin_and_fence_fb_obj(dev,
+					 to_intel_framebuffer(fb)->obj,
+					 NULL);
+	if (ret != 0) {
+		DRM_ERROR("pin & fence failed\n");
+		mutex_unlock(&dev->struct_mutex);
+		return ret;
+	}
+	old_fb = crtc->primary->fb;
+	if (old_fb)
+		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
+	mutex_unlock(&dev->struct_mutex);
+
+	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
-	return ret;
+	crtc->primary->fb = fb;
+	crtc->x = x;
+	crtc->y = y;
+
+	return 0;
 }
 
 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
@@ -6542,6 +6561,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	bool is_lvds = false;
 	struct intel_encoder *encoder;
 	struct intel_shared_dpll *pll;
+	struct drm_framebuffer *old_fb;
 	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -6619,9 +6639,27 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
 	POSTING_READ(DSPCNTR(plane));
 
-	ret = intel_pipe_set_base(crtc, x, y, fb);
+	mutex_lock(&dev->struct_mutex);
+	ret = intel_pin_and_fence_fb_obj(dev,
+					 to_intel_framebuffer(fb)->obj,
+					 NULL);
+	if (ret != 0) {
+		DRM_ERROR("pin & fence failed\n");
+		mutex_unlock(&dev->struct_mutex);
+		return ret;
+	}
+	old_fb = crtc->primary->fb;
+	if (old_fb)
+		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
+	mutex_unlock(&dev->struct_mutex);
 
-	return ret;
+	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+
+	crtc->primary->fb = fb;
+	crtc->x = x;
+	crtc->y = y;
+
+	return 0;
 }
 
 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
@@ -7097,6 +7135,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int plane = intel_crtc->plane;
+	struct drm_framebuffer *old_fb;
 	int ret;
 
 	if (!intel_ddi_pll_select(intel_crtc))
@@ -7123,9 +7162,27 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
 	POSTING_READ(DSPCNTR(plane));
 
-	ret = intel_pipe_set_base(crtc, x, y, fb);
+	mutex_lock(&dev->struct_mutex);
+	ret = intel_pin_and_fence_fb_obj(dev,
+					 to_intel_framebuffer(fb)->obj,
+					 NULL);
+	if (ret != 0) {
+		DRM_ERROR("pin & fence failed\n");
+		mutex_unlock(&dev->struct_mutex);
+		return ret;
+	}
+	old_fb = crtc->primary->fb;
+	if (old_fb)
+		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
+	mutex_unlock(&dev->struct_mutex);
 
-	return ret;
+	dev_priv->display.update_primary_plane(crtc, fb, x, y);
+
+	crtc->primary->fb = fb;
+	crtc->x = x;
+	crtc->y = y;
+
+	return 0;
 }
 
 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
-- 
1.8.1.4

[PATCH 29/66] drm/i915: Move fb pinning into __intel_set_mode

[Daniel Vetter]

Our two ->crtc_mode_set callbacks really don't care whether the fb is
pinned and set up already or not - all the state computation and
handling which originally looked at the framebuffer is already using
the indirection through the pipe configuration.

Eventually we want to move this up a bit more, but as long as the crtc
mode_set callback still exists (and as long as we don't need to pin an
entire pile of planes due to atomic modesets) there's not much point
in it. So I'll let this be for now.

v2: Don't forget about haswell ...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 80 +++++++++---------------------------
 1 file changed, 20 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a847cee2a336..cd1ec752dec4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5538,8 +5538,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	bool is_lvds = false, is_dsi = false;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
-	struct drm_framebuffer *old_fb;
-	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
 		switch (encoder->type) {
@@ -5637,26 +5635,8 @@ skip_dpll:
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
 
-	mutex_lock(&dev->struct_mutex);
-	ret = intel_pin_and_fence_fb_obj(dev,
-					 to_intel_framebuffer(fb)->obj,
-					 NULL);
-	if (ret != 0) {
-		DRM_ERROR("pin & fence failed\n");
-		mutex_unlock(&dev->struct_mutex);
-		return ret;
-	}
-	old_fb = crtc->primary->fb;
-	if (old_fb)
-		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
-	mutex_unlock(&dev->struct_mutex);
-
 	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
-	crtc->primary->fb = fb;
-	crtc->x = x;
-	crtc->y = y;
-
 	return 0;
 }
 
@@ -6561,8 +6541,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	bool is_lvds = false;
 	struct intel_encoder *encoder;
 	struct intel_shared_dpll *pll;
-	struct drm_framebuffer *old_fb;
-	int ret;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
 		switch (encoder->type) {
@@ -6639,26 +6617,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
 	POSTING_READ(DSPCNTR(plane));
 
-	mutex_lock(&dev->struct_mutex);
-	ret = intel_pin_and_fence_fb_obj(dev,
-					 to_intel_framebuffer(fb)->obj,
-					 NULL);
-	if (ret != 0) {
-		DRM_ERROR("pin & fence failed\n");
-		mutex_unlock(&dev->struct_mutex);
-		return ret;
-	}
-	old_fb = crtc->primary->fb;
-	if (old_fb)
-		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
-	mutex_unlock(&dev->struct_mutex);
-
 	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
-	crtc->primary->fb = fb;
-	crtc->x = x;
-	crtc->y = y;
-
 	return 0;
 }
 
@@ -7135,8 +7095,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int plane = intel_crtc->plane;
-	struct drm_framebuffer *old_fb;
-	int ret;
 
 	if (!intel_ddi_pll_select(intel_crtc))
 		return -EINVAL;
@@ -7162,26 +7120,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
 	POSTING_READ(DSPCNTR(plane));
 
-	mutex_lock(&dev->struct_mutex);
-	ret = intel_pin_and_fence_fb_obj(dev,
-					 to_intel_framebuffer(fb)->obj,
-					 NULL);
-	if (ret != 0) {
-		DRM_ERROR("pin & fence failed\n");
-		mutex_unlock(&dev->struct_mutex);
-		return ret;
-	}
-	old_fb = crtc->primary->fb;
-	if (old_fb)
-		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
-	mutex_unlock(&dev->struct_mutex);
-
 	dev_priv->display.update_primary_plane(crtc, fb, x, y);
 
-	crtc->primary->fb = fb;
-	crtc->x = x;
-	crtc->y = y;
-
 	return 0;
 }
 
@@ -10025,6 +9965,26 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	 * on the DPLL.
 	 */
 	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
+		struct drm_framebuffer *old_fb;
+
+		mutex_lock(&dev->struct_mutex);
+		ret = intel_pin_and_fence_fb_obj(dev,
+						 to_intel_framebuffer(fb)->obj,
+						 NULL);
+		if (ret != 0) {
+			DRM_ERROR("pin & fence failed\n");
+			mutex_unlock(&dev->struct_mutex);
+			goto done;
+		}
+		old_fb = crtc->primary->fb;
+		if (old_fb)
+			intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
+		mutex_unlock(&dev->struct_mutex);
+
+		crtc->primary->fb = fb;
+		crtc->x = x;
+		crtc->y = y;
+
 		ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
 						      x, y, fb);
 		if (ret)
-- 
1.8.1.4

[PATCH 30/66] drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set

[Daniel Vetter]

All these functions simply convert sw state as encoded in the pipe
config or primary framebuffer into hardware state. So we can move them
all into the crtc enable hook. Unfortunately this means a little bit
of duplication between the i9xx and vlv functions, but since we
already have highly refactored code I think this is acceptable.

Also a pile of forward declarations unfortunately.

Note also that the various <platform>_update_pll functions are still
called from within the ->crtc_mode_set hook. Mostly they compute the
clock state for the pipe config, but unfortunately there are some
random register writes interspersed. Those need to be moved out first
before we can enable runtime PM for DPMS.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 94 ++++++++++++++++++++++--------------
 1 file changed, 59 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cd1ec752dec4..5740e08c3d2e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -55,6 +55,9 @@ static int intel_framebuffer_init(struct drm_device *dev,
 				  struct intel_framebuffer *ifb,
 				  struct drm_mode_fb_cmd2 *mode_cmd,
 				  struct drm_i915_gem_object *obj);
+static void intel_dp_set_m_n(struct intel_crtc *crtc);
+static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
+static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 
 typedef struct {
 	int	min, max;
@@ -4313,12 +4316,37 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	bool is_dsi;
+	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
 	if (intel_crtc->active)
 		return;
 
+	/* Set up the display plane register */
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
+	intel_set_pipe_timings(intel_crtc);
+
+	/* pipesrc and dspsize control the size that is scaled from,
+	 * which should always be the user's requested size.
+	 */
+	I915_WRITE(DSPSIZE(plane),
+		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+		   (intel_crtc->config.pipe_src_w - 1));
+	I915_WRITE(DSPPOS(plane), 0);
+
+	i9xx_set_pipeconf(intel_crtc);
+
+	I915_WRITE(DSPCNTR(plane), dspcntr);
+	POSTING_READ(DSPCNTR(plane));
+
+	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
+					       crtc->x, crtc->y);
+
 	intel_crtc->active = true;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4366,12 +4394,42 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
+	u32 dspcntr;
 
 	WARN_ON(!crtc->enabled);
 
 	if (intel_crtc->active)
 		return;
 
+	/* Set up the display plane register */
+	dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+	if (pipe == 0)
+		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
+	else
+		dspcntr |= DISPPLANE_SEL_PIPE_B;
+
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
+	intel_set_pipe_timings(intel_crtc);
+
+	/* pipesrc and dspsize control the size that is scaled from,
+	 * which should always be the user's requested size.
+	 */
+	I915_WRITE(DSPSIZE(plane),
+		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+		   (intel_crtc->config.pipe_src_w - 1));
+	I915_WRITE(DSPPOS(plane), 0);
+
+	i9xx_set_pipeconf(intel_crtc);
+
+	I915_WRITE(DSPCNTR(plane), dspcntr);
+	POSTING_READ(DSPCNTR(plane));
+
+	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
+					       crtc->x, crtc->y);
+
 	intel_crtc->active = true;
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -5529,11 +5587,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
-	u32 dspcntr;
 	bool ok, has_reduced_clock = false;
 	bool is_lvds = false, is_dsi = false;
 	struct intel_encoder *encoder;
@@ -5553,7 +5608,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	}
 
 	if (is_dsi)
-		goto skip_dpll;
+		return 0;
 
 	if (!intel_crtc->config.clock_set) {
 		refclk = i9xx_get_refclk(crtc, num_connectors);
@@ -5606,37 +5661,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                                 num_connectors);
 	}
 
-skip_dpll:
-	/* Set up the display plane register */
-	dspcntr = DISPPLANE_GAMMA_ENABLE;
-
-	if (!IS_VALLEYVIEW(dev)) {
-		if (pipe == 0)
-			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
-		else
-			dspcntr |= DISPPLANE_SEL_PIPE_B;
-	}
-
-	if (intel_crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
-
-	intel_set_pipe_timings(intel_crtc);
-
-	/* pipesrc and dspsize control the size that is scaled from,
-	 * which should always be the user's requested size.
-	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
-		   (intel_crtc->config.pipe_src_w - 1));
-	I915_WRITE(DSPPOS(plane), 0);
-
-	i9xx_set_pipeconf(intel_crtc);
-
-	I915_WRITE(DSPCNTR(plane), dspcntr);
-	POSTING_READ(DSPCNTR(plane));
-
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
-
 	return 0;
 }
 
-- 
1.8.1.4

[PATCH 31/66] drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set

[Daniel Vetter]

Now this really should be in the pipe config somewhere, but till now
it isn't. We can at least move it up a bit next to all the other pll
code since intel_dp_set_m_n really doesn't depend upon this.

This is just prep work so that moving all the hw frobbing code from
->crtc_mode_set to ->crtc_enable is clean.

v2: Do the same for haswell while at it, not just for ivb.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5740e08c3d2e..d6878d07a516 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6620,14 +6620,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	} else
 		intel_put_shared_dpll(intel_crtc);
 
-	if (intel_crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
-
 	if (is_lvds && has_reduced_clock && i915.powersave)
 		intel_crtc->lowfreq_avail = true;
 	else
 		intel_crtc->lowfreq_avail = false;
 
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
 	intel_set_pipe_timings(intel_crtc);
 
 	if (intel_crtc->config.has_pch_encoder) {
@@ -7124,11 +7124,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 		return -EINVAL;
 	intel_ddi_pll_enable(intel_crtc);
 
+	intel_crtc->lowfreq_avail = false;
+
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
-	intel_crtc->lowfreq_avail = false;
-
 	intel_set_pipe_timings(intel_crtc);
 
 	if (intel_crtc->config.has_pch_encoder) {
-- 
1.8.1.4

[PATCH 32/66] drm/i915: Shovel hw setup code out of ilk_crtc_mode_set

[Daniel Vetter]

Again this code just transforms sw state from the pipe config into
hardware state, so we can just move it around. Unfortunately again a
few forward declarations since intel_display.c is becoming a bit of a
mess.

Note that both for i9xx and ironlake code the only things remaining in
the ->crtc_mode_set hook is now the clock state computation and
sharing code. That needs to be moved into the compute config stage so
that we can catch impossible configurations earlier.

Also note that some of the DPLL hw setup code is still run from within
->crtc_mode_set, namele the pll->mode_set callback. We need to move
that first before we can do fancy things like enable runtime PM for
dpms off.

v2: Make it compile again after the rebase, bisectability issue
reported by Wu Fengguang.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6878d07a516..a8a2281c8179 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -58,6 +58,9 @@ static int intel_framebuffer_init(struct drm_device *dev,
 static void intel_dp_set_m_n(struct intel_crtc *crtc);
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
+static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+					 struct intel_link_m_n *m_n);
+static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 
 typedef struct {
 	int	min, max;
@@ -3680,12 +3683,32 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
+	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
 	if (intel_crtc->active)
 		return;
 
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
+	intel_set_pipe_timings(intel_crtc);
+
+	if (intel_crtc->config.has_pch_encoder) {
+		intel_cpu_transcoder_set_m_n(intel_crtc,
+					     &intel_crtc->config.fdi_m_n);
+	}
+
+	ironlake_set_pipeconf(crtc);
+
+	/* Set up the display plane register */
+	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
+	POSTING_READ(DSPCNTR(plane));
+
+	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
+					       crtc->x, crtc->y);
+
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -6554,10 +6577,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 				  struct drm_framebuffer *fb)
 {
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int pipe = intel_crtc->pipe;
-	int plane = intel_crtc->plane;
 	int num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll = 0, fp = 0, fp2 = 0;
@@ -6614,7 +6634,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		pll = intel_get_shared_dpll(intel_crtc);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
-					 pipe_name(pipe));
+					 pipe_name(intel_crtc->pipe));
 			return -EINVAL;
 		}
 	} else
@@ -6625,24 +6645,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	else
 		intel_crtc->lowfreq_avail = false;
 
-	if (intel_crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
-
-	intel_set_pipe_timings(intel_crtc);
-
-	if (intel_crtc->config.has_pch_encoder) {
-		intel_cpu_transcoder_set_m_n(intel_crtc,
-					     &intel_crtc->config.fdi_m_n);
-	}
-
-	ironlake_set_pipeconf(crtc);
-
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
-
 	return 0;
 }
 
-- 
1.8.1.4

[PATCH 33/66] drm/i915: Shovel hw setup code out of hsw_crtc_mode_set

[Daniel Vetter]

Again the same story: This code just transform sw state from the pipe
config into hardware state. And again we can't move the pll code, but
this time around because the state isn't properly tracked in the pipe
config.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++------------------
 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8a2281c8179..b6dbb6c4c1fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -61,6 +61,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 					 struct intel_link_m_n *m_n);
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
+static void haswell_set_pipeconf(struct drm_crtc *crtc);
+static void intel_set_pipe_csc(struct drm_crtc *crtc);
 
 typedef struct {
 	int	min, max;
@@ -3805,12 +3807,34 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe;
+	enum plane plane = intel_crtc->plane;
 
 	WARN_ON(!crtc->enabled);
 
 	if (intel_crtc->active)
 		return;
 
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
+	intel_set_pipe_timings(intel_crtc);
+
+	if (intel_crtc->config.has_pch_encoder) {
+		intel_cpu_transcoder_set_m_n(intel_crtc,
+					     &intel_crtc->config.fdi_m_n);
+	}
+
+	haswell_set_pipeconf(crtc);
+
+	intel_set_pipe_csc(crtc);
+
+	/* Set up the display plane register */
+	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
+	POSTING_READ(DSPCNTR(plane));
+
+	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
+					       crtc->x, crtc->y);
+
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
@@ -7117,10 +7141,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 				 int x, int y,
 				 struct drm_framebuffer *fb)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int plane = intel_crtc->plane;
 
 	if (!intel_ddi_pll_select(intel_crtc))
 		return -EINVAL;
@@ -7128,26 +7149,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_crtc->lowfreq_avail = false;
 
-	if (intel_crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
-
-	intel_set_pipe_timings(intel_crtc);
-
-	if (intel_crtc->config.has_pch_encoder) {
-		intel_cpu_transcoder_set_m_n(intel_crtc,
-					     &intel_crtc->config.fdi_m_n);
-	}
-
-	haswell_set_pipeconf(crtc);
-
-	intel_set_pipe_csc(crtc);
-
-	/* Set up the display plane register */
-	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
-	POSTING_READ(DSPCNTR(plane));
-
-	dev_priv->display.update_primary_plane(crtc, fb, x, y);
-
 	return 0;
 }
 
-- 
1.8.1.4

[PATCH 34/66] drm/i915: Extract i9xx_set_pll_dividers

[Daniel Vetter]

These two writes are the very last hw writes from the
->crtc_modeset_callback on pre-gen5 hardware. As usual vlv is a bit
different, so this here is just warm-up.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b6dbb6c4c1fb..057f4d6a3e1f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4433,6 +4433,15 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	drm_vblank_on(dev, pipe);
 }
 
+static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
+	I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
+}
+
 static void i9xx_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -4448,6 +4457,8 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->active)
 		return;
 
+	i9xx_set_pll_dividers(intel_crtc);
+
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
@@ -5112,8 +5123,6 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 				     intel_clock_t *reduced_clock)
 {
 	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int pipe = crtc->pipe;
 	u32 fp, fp2 = 0;
 
 	if (IS_PINEVIEW(dev)) {
@@ -5126,17 +5135,14 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 			fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
 
-	I915_WRITE(FP0(pipe), fp);
 	crtc->config.dpll_hw_state.fp0 = fp;
 
 	crtc->lowfreq_avail = false;
 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
 	    reduced_clock && i915.powersave) {
-		I915_WRITE(FP1(pipe), fp2);
 		crtc->config.dpll_hw_state.fp1 = fp2;
 		crtc->lowfreq_avail = true;
 	} else {
-		I915_WRITE(FP1(pipe), fp);
 		crtc->config.dpll_hw_state.fp1 = fp;
 	}
 }
-- 
1.8.1.4

[PATCH 35/66] drm/i915: Extract vlv_prepare_pll

[Daniel Vetter]

With this all hw writes are also gone from the ->crtc_mode_set hook on
vlv. I wondered whether we should track more of the pll state in the
pipe config, but otoh as long as we don't have shared plls that's not
really useful - the cross-checking of the port clock should be
sufficient.

While at it also de-magic some of the pipe checks, this has been
irking me since a long time.

Whit this vlv is now ready for runtime PM on dpms. If we'd have
runtime PM support in general ...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 53 ++++++++++++++++++++----------------
 1 file changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 057f4d6a3e1f..21e20bc495ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -63,6 +63,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
+static void vlv_prepare_pll(struct intel_crtc *crtc);
 
 typedef struct {
 	int	min, max;
@@ -4370,6 +4371,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->active)
 		return;
 
+	vlv_prepare_pll(intel_crtc);
+
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
@@ -5220,12 +5223,34 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
 
 static void vlv_update_pll(struct intel_crtc *crtc)
 {
+	u32 dpll, dpll_md;
+
+	/*
+	 * Enable DPIO clock input. We should never disable the reference
+	 * clock for pipe B, since VGA hotplug / manual detection depends
+	 * on it.
+	 */
+	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
+		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+	/* We should never disable this, set it here for state tracking */
+	if (crtc->pipe == PIPE_B)
+		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+	dpll |= DPLL_VCO_ENABLE;
+	crtc->config.dpll_hw_state.dpll = dpll;
+
+	dpll_md = (crtc->config.pixel_multiplier - 1)
+		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
+	crtc->config.dpll_hw_state.dpll_md = dpll_md;
+}
+
+static void vlv_prepare_pll(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = crtc->pipe;
-	u32 dpll, mdiv;
+	u32 mdiv;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	u32 coreclk, reg_val, dpll_md;
+	u32 coreclk, reg_val;
 
 	mutex_lock(&dev_priv->dpio_lock);
 
@@ -5238,7 +5263,7 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	/* See eDP HDMI DPIO driver vbios notes doc */
 
 	/* PLL B needs special handling */
-	if (pipe)
+	if (pipe == PIPE_B)
 		vlv_pllb_recal_opamp(dev_priv, pipe);
 
 	/* Set up Tx target for periodic Rcomp update */
@@ -5282,7 +5307,7 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
 	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
 		/* Use SSC source */
-		if (!pipe)
+		if (pipe == PIPE_A)
 			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
 					 0x0df40000);
 		else
@@ -5290,7 +5315,7 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 					 0x0df70000);
 	} else { /* HDMI or VGA */
 		/* Use bend source */
-		if (!pipe)
+		if (pipe == PIPE_A)
 			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
 					 0x0df70000);
 		else
@@ -5306,24 +5331,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
 
 	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
-
-	/*
-	 * Enable DPIO clock input. We should never disable the reference
-	 * clock for pipe B, since VGA hotplug / manual detection depends
-	 * on it.
-	 */
-	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
-		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
-	/* We should never disable this, set it here for state tracking */
-	if (pipe == PIPE_B)
-		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-	dpll |= DPLL_VCO_ENABLE;
-	crtc->config.dpll_hw_state.dpll = dpll;
-
-	dpll_md = (crtc->config.pixel_multiplier - 1)
-		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
-	crtc->config.dpll_hw_state.dpll_md = dpll_md;
-
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
-- 
1.8.1.4

[PATCH 36/66] drm/i915: Only update shared dpll state when needed

[Daniel Vetter]

Instead of every time it isn't active: We only need to do that when
the pll is currently unused, i.e. when pll->refcount == 0. For
paranoia add a warning for the ibx case where plls have a fixed
mapping and hence should always be unused after the call to
intel_put_shared_dpll.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21e20bc495ee..aef869dcc054 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3416,6 +3416,11 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
 			      crtc->base.base.id, pll->name);
 
+		WARN_ON(pll->refcount);
+
+		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
+		       sizeof(pll->hw_state));
+
 		goto found;
 	}
 
@@ -3442,6 +3447,10 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 		if (pll->refcount == 0) {
 			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
 				      crtc->base.base.id, pll->name);
+
+			memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
+			       sizeof(pll->hw_state));
+
 			goto found;
 		}
 	}
@@ -3454,9 +3463,6 @@ found:
 			 pipe_name(crtc->pipe));
 
 	if (pll->active == 0) {
-		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
-		       sizeof(pll->hw_state));
-
 		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll);
-- 
1.8.1.4

[PATCH 37/66] drm/i915: Extract intel_prepare_shared_dpll

[Daniel Vetter]

This is the last piece of code which write state to the hardware in
the ironalake ->crtc_mode_set callback.

I think we could merge this with the pll->enable hook, but otoh the
ordering requirements with the ldvs port are really tricky. Doing the
FP0/1 writes up-front before we even prepare the lvds port (in the
pre_pll_enable hook) like on i9xx seems safest.

With this ilk+ platforms are now ready for runtime PM with DPMS. Since
hsw/bdw also support runtime pm besides snb we need to first make the
haswell code save before we can touch the core code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aef869dcc054..96bab640399f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1551,6 +1551,22 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 		     port_name(dport->port), I915_READ(DPLL(0)));
 }
 
+static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+
+	WARN_ON(!pll->refcount);
+	if (pll->active == 0) {
+		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
+		WARN_ON(pll->on);
+		assert_shared_dpll_disabled(dev_priv, pll);
+
+		pll->mode_set(dev_priv, pll);
+	}
+}
+
 /**
  * ironlake_enable_shared_dpll - enable PCH PLL
  * @dev_priv: i915 private structure
@@ -3462,13 +3478,6 @@ found:
 	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
 			 pipe_name(crtc->pipe));
 
-	if (pll->active == 0) {
-		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
-		WARN_ON(pll->on);
-		assert_shared_dpll_disabled(dev_priv, pll);
-
-		pll->mode_set(dev_priv, pll);
-	}
 	pll->refcount++;
 
 	return pll;
@@ -3699,6 +3708,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->active)
 		return;
 
+	if (intel_crtc->config.has_pch_encoder)
+		intel_prepare_shared_dpll(intel_crtc);
+
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
-- 
1.8.1.4

[PATCH 38/66] drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

[Daniel Vetter]

Besides the fairly useless BUG_ON the logic is completely generic
and cane be used on any platform what wants to reuse the shared
dpll support code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 96bab640399f..1513d9fceebe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1568,21 +1568,19 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 }
 
 /**
- * ironlake_enable_shared_dpll - enable PCH PLL
+ * intel_enable_shared_dpll - enable PCH PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
  *
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
-static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
+static void intel_enable_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
-	/* PCH PLLs only available on ILK, SNB and IVB */
-	BUG_ON(INTEL_INFO(dev)->gen < 5);
 	if (WARN_ON(pll == NULL))
 		return;
 
@@ -3328,7 +3326,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	 * Note that enable_shared_dpll tries to do the right thing, but
 	 * get_shared_dpll unconditionally resets the pll - we need that to have
 	 * the right LVDS enable sequence. */
-	ironlake_enable_shared_dpll(intel_crtc);
+	intel_enable_shared_dpll(intel_crtc);
 
 	/* set transcoder timing, panel must allow it */
 	assert_panel_unlocked(dev_priv, pipe);
-- 
1.8.1.4

[PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

[Daniel Vetter]

All the other checks also check hw state, so checking our software
refcounts for the plls looks a bit odd. Also this will simplify the
conversion over to the shared dpll framework, which itself has massive
amounts of checks to make sure that we never leave a display pll
enabled when we shouldn't.

So after that conversion we should stil have a good enough coverage of
asserts for entering pc8/runtime pm on hsw/bdw.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1513d9fceebe..22b3d74f9ecc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6926,7 +6926,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
-	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 	struct intel_crtc *crtc;
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
@@ -6934,9 +6933,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 		     pipe_name(crtc->pipe));
 
 	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
-	WARN(plls->spll_refcount, "SPLL enabled\n");
-	WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
-	WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
+	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
+	WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
+	WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
 	WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
 	WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
 	     "CPU PWM1 enabled\n");
-- 
1.8.1.4

[PATCH 40/66] drm/i915: Remove spll_refcount for hsw

[Daniel Vetter]

SPLL would be a reference clock we could potentially share,
especially if we want to use the SSC mode. But currently we
don't, so let's rip out this complexity for a simpler conversion
to the new display pll framework.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 -
 drivers/gpu/drm/i915/intel_ddi.c | 41 +++++++++++++---------------------------
 2 files changed, 13 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e6c16068010f..b6eac92e0a22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -221,7 +221,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
 			    struct intel_link_m_n *m_n);
 
 struct intel_ddi_plls {
-	int spll_refcount;
 	int wrpll1_refcount;
 	int wrpll2_refcount;
 };
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 271ce19ee880..16ec6aee3df7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -394,14 +394,11 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 
 	switch (intel_crtc->ddi_pll_sel) {
 	case PORT_CLK_SEL_SPLL:
-		plls->spll_refcount--;
-		if (plls->spll_refcount == 0) {
-			DRM_DEBUG_KMS("Disabling SPLL\n");
-			val = I915_READ(SPLL_CTL);
-			WARN_ON(!(val & SPLL_PLL_ENABLE));
-			I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
-			POSTING_READ(SPLL_CTL);
-		}
+		DRM_DEBUG_KMS("Disabling SPLL\n");
+		val = I915_READ(SPLL_CTL);
+		WARN_ON(!(val & SPLL_PLL_ENABLE));
+		I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
+		POSTING_READ(SPLL_CTL);
 		break;
 	case PORT_CLK_SEL_WRPLL1:
 		plls->wrpll1_refcount--;
@@ -425,7 +422,6 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 		break;
 	}
 
-	WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
 	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 
@@ -821,16 +817,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 		}
 
 	} else if (type == INTEL_OUTPUT_ANALOG) {
-		if (plls->spll_refcount == 0) {
-			DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
-				      pipe_name(pipe));
-			plls->spll_refcount++;
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
-		} else {
-			DRM_ERROR("SPLL already in use\n");
-			return false;
-		}
-
+		DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
+			      pipe_name(pipe));
+		intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 	} else {
 		WARN(1, "Invalid DDI encoder type %d\n", type);
 		return false;
@@ -869,13 +858,13 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 		return;
 
 	case PORT_CLK_SEL_SPLL:
-		pll_name = "SPLL";
-		reg = SPLL_CTL;
-		refcount = plls->spll_refcount;
 		new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
 			  SPLL_PLL_SSC;
-		break;
-
+		WARN(I915_READ(SPLL_CTL) & enable_bit, "SPLL already enabled\n");
+		I915_WRITE(SPLL_CTL, new_val);
+		POSTING_READ(SPLL_CTL);
+		udelay(20);
+		return;
 	case PORT_CLK_SEL_WRPLL1:
 	case PORT_CLK_SEL_WRPLL2:
 		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
@@ -1186,7 +1175,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
 	enum pipe pipe;
 	struct intel_crtc *intel_crtc;
 
-	dev_priv->ddi_plls.spll_refcount = 0;
 	dev_priv->ddi_plls.wrpll1_refcount = 0;
 	dev_priv->ddi_plls.wrpll2_refcount = 0;
 
@@ -1203,9 +1191,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
 								 pipe);
 
 		switch (intel_crtc->ddi_pll_sel) {
-		case PORT_CLK_SEL_SPLL:
-			dev_priv->ddi_plls.spll_refcount++;
-			break;
 		case PORT_CLK_SEL_WRPLL1:
 			dev_priv->ddi_plls.wrpll1_refcount++;
 			break;
-- 
1.8.1.4

[PATCH 41/66] drm/i915: Clean up WRPLL/SPLL #defines

[Daniel Vetter]

Luckily the bit definitions match, but it's still confusing
to use one when handling the other. So sprinkle some OCD over
the #defines to make them match and use the right version in
each place.

Maybe we should unify these definitions completely, but that
can always be done sometime in the future.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 ++++---
 drivers/gpu/drm/i915/intel_ddi.c | 12 ++++++------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f845556503e..64d40f22e708 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5505,9 +5505,10 @@ enum punit_power_well {
 #define WRPLL_CTL1			0x46040
 #define WRPLL_CTL2			0x46060
 #define  WRPLL_PLL_ENABLE		(1<<31)
-#define  WRPLL_PLL_SELECT_SSC		(0x01<<28)
-#define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)
-#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
+#define  WRPLL_PLL_SSC			(1<<28)
+#define  WRPLL_PLL_NON_SSC		(2<<28)
+#define  WRPLL_PLL_LCPLL		(3<<28)
+#define  WRPLL_PLL_REF_MASK		(3<<28)
 /* WRPLL divider programming */
 #define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)
 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 16ec6aee3df7..09ae104d9c2b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -588,9 +588,9 @@ static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 	u32 wrpll;
 
 	wrpll = I915_READ(reg);
-	switch (wrpll & SPLL_PLL_REF_MASK) {
-	case SPLL_PLL_SSC:
-	case SPLL_PLL_NON_SSC:
+	switch (wrpll & WRPLL_PLL_REF_MASK) {
+	case WRPLL_PLL_SSC:
+	case WRPLL_PLL_NON_SSC:
 		/*
 		 * We could calculate spread here, but our checking
 		 * code only cares about 5% accuracy, and spread is a max of
@@ -598,7 +598,7 @@ static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 		 */
 		refclk = 135;
 		break;
-	case SPLL_PLL_LCPLL:
+	case WRPLL_PLL_LCPLL:
 		refclk = LC_FREQ;
 		break;
 	default:
@@ -780,7 +780,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 
 		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 
-		val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
+		val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		      WRPLL_DIVIDER_POST(p);
 
@@ -879,7 +879,7 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 
 		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 
-		new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
+		new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 			  WRPLL_DIVIDER_REFERENCE(r2) |
 			  WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
 
-- 
1.8.1.4

[PATCH 42/66] drm/i915: Make intel_wait_for_pipe_off static

[Daniel Vetter]

Noticed while reading around.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_drv.h     | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22b3d74f9ecc..713563faeafd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -854,7 +854,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
  *   ends up stopping at the start of the next frame).
  *
  */
-void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
+static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c85f5e5ddc7c..2be0b104fbec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -719,7 +719,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 					     enum pipe pipe);
 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
-void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 			 struct intel_digital_port *dport);
-- 
1.8.1.4

[PATCH 43/66] drm/i915: Disable pipe before ports on ilk

[Daniel Vetter]

The modeset sequence docs are very clear that we should disable the
pipe before we switch off any ports, for both pch ports and the cpu
edp port.

In practice it doesn't seem to matter too much since for non-DP pch
ports it only matters that the pch transcoder is still on. And for cpu
edp ports it either doesn't seem to matter or we're quick enough.

But for DP pch ports we have a regular stream of bug reports where the
cpu pipe seems to be stuck and won't turn off. This change should
address this.

This should also help with using a nuclear pageflip atomically switch
off all planes, since it moves that ahead of any other disabling
action.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=62251
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52061
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54687
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67462
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 713563faeafd..82ad84eefc8d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3924,14 +3924,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	ilk_crtc_disable_planes(crtc);
 
-	for_each_encoder_on_crtc(dev, crtc, encoder)
-		encoder->disable(encoder);
-
 	if (intel_crtc->config.has_pch_encoder)
 		intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
 
 	intel_disable_pipe(dev_priv, pipe);
 
+	for_each_encoder_on_crtc(dev, crtc, encoder)
+		encoder->disable(encoder);
+
 	ironlake_pfit_disable(intel_crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
-- 
1.8.1.4

[PATCH 44/66] drm/i915: Pass port explicitly to intel_ddi_get_hw_state

[Daniel Vetter]

Well, the newly created intel_ddi_get_port_state.

In general intel_ddi.c has way too intimate knowledge with everyone
else as exemplified with all the encoder/connector noodling and the
massive exported function list.

As a first step explictly pass around the port, first in the encoder
callback.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c |  8 +++++++-
 drivers/gpu/drm/i915/intel_ddi.c | 13 ++++++++++---
 drivers/gpu/drm/i915/intel_drv.h |  3 ++-
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 22d8347f7838..f34d1df88918 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -137,6 +137,12 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
 	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
 }
 
+static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
+				 enum pipe *pipe)
+{
+	return intel_ddi_get_port_state(encoder, pipe, PORT_E);
+}
+
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -858,7 +864,7 @@ void intel_crt_init(struct drm_device *dev)
 		crt->base.hpd_pin = HPD_CRT;
 	if (HAS_DDI(dev)) {
 		crt->base.get_config = hsw_crt_get_config;
-		crt->base.get_hw_state = intel_ddi_get_hw_state;
+		crt->base.get_hw_state = hsw_crt_get_hw_state;
 	} else {
 		crt->base.get_config = intel_crt_get_config;
 		crt->base.get_hw_state = intel_crt_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 09ae104d9c2b..ace43c6a6fa4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1082,12 +1082,11 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 	}
 }
 
-bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
-			    enum pipe *pipe)
+bool intel_ddi_get_port_state(struct intel_encoder *encoder,
+			      enum pipe *pipe, enum port port)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	enum port port = intel_ddi_get_encoder_port(encoder);
 	enum intel_display_power_domain power_domain;
 	u32 tmp;
 	int i;
@@ -1135,6 +1134,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	return false;
 }
 
+static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
+				   enum pipe *pipe)
+{
+	enum port port = intel_ddi_get_encoder_port(encoder);
+
+	return intel_ddi_get_port_state(encoder, pipe, port);
+}
+
 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
 				       enum pipe pipe)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2be0b104fbec..ba727b11014a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -671,7 +671,8 @@ void intel_prepare_ddi(struct drm_device *dev);
 void hsw_fdi_link_train(struct drm_crtc *crtc);
 void intel_ddi_init(struct drm_device *dev, enum port port);
 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
-bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
+bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
+			      enum port port);
 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 void intel_ddi_pll_init(struct drm_device *dev);
 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
-- 
1.8.1.4

[PATCH 45/66] drm/i915: Unexport intel_ddi_connector_get_hw_state

[Daniel Vetter]

The connector->get_hw_state function is actually platform dependent.
So move it out of the shared connector init functions. This allows us
to drop another intel_ddi.c export.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c  | 10 +++++++---
 drivers/gpu/drm/i915/intel_dp.c   |  5 +----
 drivers/gpu/drm/i915/intel_drv.h  |  1 -
 drivers/gpu/drm/i915/intel_hdmi.c |  5 +----
 4 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ace43c6a6fa4..afa1e87c54cc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1037,7 +1037,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 	I915_WRITE(reg, val);
 }
 
-bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
+static bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 {
 	struct drm_device *dev = intel_connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1689,13 +1689,17 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	intel_encoder->cloneable = 0;
 	intel_encoder->hot_plug = intel_ddi_hot_plug;
 
-	if (init_dp)
+	if (init_dp) {
 		dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
+		dp_connector->get_hw_state = intel_ddi_connector_get_hw_state;
+	}
 
 	/* In theory we don't need the encoder->type check, but leave it just in
 	 * case we have some really bad VBTs... */
-	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
+	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
 		hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
+		hdmi_connector->get_hw_state = intel_ddi_connector_get_hw_state;
+	}
 
 	if (!dp_connector && !hdmi_connector) {
 		drm_encoder_cleanup(encoder);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5746fe22dde3..ca94be9554f4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3931,10 +3931,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_connector_attach_encoder(intel_connector, intel_encoder);
 	drm_sysfs_connector_add(connector);
 
-	if (HAS_DDI(dev))
-		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
-	else
-		intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_dp_connector_unregister;
 
 	/* Set up the hotplug pin. */
@@ -4043,4 +4039,5 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		kfree(intel_dig_port);
 		kfree(intel_connector);
 	}
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ba727b11014a..1c093e71db7d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -686,7 +686,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc);
 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 void intel_ddi_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_config *pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ced93bd33f80..b748bb39347c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1328,10 +1328,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_hdmi->set_infoframes = cpt_set_infoframes;
 	}
 
-	if (HAS_DDI(dev))
-		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
-	else
-		intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_connector_unregister;
 
 	intel_hdmi_add_properties(intel_hdmi, connector);
@@ -1400,4 +1396,5 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	intel_dig_port->dp.output_reg = 0;
 
 	intel_hdmi_init_connector(intel_dig_port, intel_connector);
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
 }
-- 
1.8.1.4

[PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

[Daniel Vetter]

The pch encoder case really isn't anything generic on hsw:
- It's for the vga port only and
- the vga port does only exist on some hsw platforms.

Imo it helps the generic code flow a lot if we shovel all this into
hsw specific enable/disable hooks. A bonus is that some of our largest
files (intel_ddi.c and intel_display.c) will lose a pile of really big
functions.

Step one is to move the fdi link training code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 136 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     | 134 +---------------------------------
 drivers/gpu/drm/i915/intel_display.c |   4 --
 drivers/gpu/drm/i915/intel_drv.h     |   3 +-
 4 files changed, 140 insertions(+), 137 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index f34d1df88918..2d8f4fe1b450 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -143,6 +143,141 @@ static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
 	return intel_ddi_get_port_state(encoder, pipe, PORT_E);
 }
 
+static const long hsw_ddi_buf_ctl_values[] = {
+	DDI_BUF_EMP_400MV_0DB_HSW,
+	DDI_BUF_EMP_400MV_3_5DB_HSW,
+	DDI_BUF_EMP_400MV_6DB_HSW,
+	DDI_BUF_EMP_400MV_9_5DB_HSW,
+	DDI_BUF_EMP_600MV_0DB_HSW,
+	DDI_BUF_EMP_600MV_3_5DB_HSW,
+	DDI_BUF_EMP_600MV_6DB_HSW,
+	DDI_BUF_EMP_800MV_0DB_HSW,
+	DDI_BUF_EMP_800MV_3_5DB_HSW
+};
+
+static void hsw_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	u32 temp, i, rx_ctl_val;
+
+	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
+	 * mode set "sequence for CRT port" document:
+	 * - TP1 to TP2 time with the default value
+	 * - FDI delay to 90h
+	 *
+	 * WaFDIAutoLinkSetTimingOverrride:hsw
+	 */
+	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
+				  FDI_RX_PWRDN_LANE0_VAL(2) |
+				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
+
+	/* Enable the PCH Receiver FDI PLL */
+	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+		     FDI_RX_PLL_ENABLE |
+		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
+	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+	POSTING_READ(_FDI_RXA_CTL);
+	udelay(220);
+
+	/* Switch from Rawclk to PCDclk */
+	rx_ctl_val |= FDI_PCDCLK;
+	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+
+	/* Configure Port Clock Select */
+	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
+
+	/* Start the training iterating through available voltages and emphasis,
+	 * testing each value twice. */
+	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
+		/* Configure DP_TP_CTL with auto-training */
+		I915_WRITE(DP_TP_CTL(PORT_E),
+					DP_TP_CTL_FDI_AUTOTRAIN |
+					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+					DP_TP_CTL_LINK_TRAIN_PAT1 |
+					DP_TP_CTL_ENABLE);
+
+		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
+		 * DDI E does not support port reversal, the functionality is
+		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
+		 * port reversal bit */
+		I915_WRITE(DDI_BUF_CTL(PORT_E),
+			   DDI_BUF_CTL_ENABLE |
+			   ((intel_crtc->config.fdi_lanes - 1) << 1) |
+			   hsw_ddi_buf_ctl_values[i / 2]);
+		POSTING_READ(DDI_BUF_CTL(PORT_E));
+
+		udelay(600);
+
+		/* Program PCH FDI Receiver TU */
+		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
+
+		/* Enable PCH FDI Receiver with auto-training */
+		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
+		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+		POSTING_READ(_FDI_RXA_CTL);
+
+		/* Wait for FDI receiver lane calibration */
+		udelay(30);
+
+		/* Unset FDI_RX_MISC pwrdn lanes */
+		temp = I915_READ(_FDI_RXA_MISC);
+		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+		I915_WRITE(_FDI_RXA_MISC, temp);
+		POSTING_READ(_FDI_RXA_MISC);
+
+		/* Wait for FDI auto training time */
+		udelay(5);
+
+		temp = I915_READ(DP_TP_STATUS(PORT_E));
+		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
+			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
+
+			/* Enable normal pixel sending for FDI */
+			I915_WRITE(DP_TP_CTL(PORT_E),
+				   DP_TP_CTL_FDI_AUTOTRAIN |
+				   DP_TP_CTL_LINK_TRAIN_NORMAL |
+				   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+				   DP_TP_CTL_ENABLE);
+
+			return;
+		}
+
+		temp = I915_READ(DDI_BUF_CTL(PORT_E));
+		temp &= ~DDI_BUF_CTL_ENABLE;
+		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
+		POSTING_READ(DDI_BUF_CTL(PORT_E));
+
+		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
+		temp = I915_READ(DP_TP_CTL(PORT_E));
+		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
+		I915_WRITE(DP_TP_CTL(PORT_E), temp);
+		POSTING_READ(DP_TP_CTL(PORT_E));
+
+		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+
+		rx_ctl_val &= ~FDI_RX_ENABLE;
+		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
+		POSTING_READ(_FDI_RXA_CTL);
+
+		/* Reset FDI_RX_MISC pwrdn lanes */
+		temp = I915_READ(_FDI_RXA_MISC);
+		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+		I915_WRITE(_FDI_RXA_MISC, temp);
+		POSTING_READ(_FDI_RXA_MISC);
+	}
+
+	DRM_ERROR("FDI link training failed!\n");
+}
+
+static void hsw_crt_pre_enable(struct intel_encoder *encoder)
+{
+	hsw_fdi_link_train(encoder->base.crtc);
+}
+
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -865,6 +1000,7 @@ void intel_crt_init(struct drm_device *dev)
 	if (HAS_DDI(dev)) {
 		crt->base.get_config = hsw_crt_get_config;
 		crt->base.get_hw_state = hsw_crt_get_hw_state;
+		crt->base.pre_enable = hsw_crt_pre_enable;
 	} else {
 		crt->base.get_config = intel_crt_get_config;
 		crt->base.get_hw_state = intel_crt_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index afa1e87c54cc..13abde3e848f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -211,20 +211,8 @@ void intel_prepare_ddi(struct drm_device *dev)
 		intel_prepare_ddi_buffers(dev, port);
 }
 
-static const long hsw_ddi_buf_ctl_values[] = {
-	DDI_BUF_EMP_400MV_0DB_HSW,
-	DDI_BUF_EMP_400MV_3_5DB_HSW,
-	DDI_BUF_EMP_400MV_6DB_HSW,
-	DDI_BUF_EMP_400MV_9_5DB_HSW,
-	DDI_BUF_EMP_600MV_0DB_HSW,
-	DDI_BUF_EMP_600MV_3_5DB_HSW,
-	DDI_BUF_EMP_600MV_6DB_HSW,
-	DDI_BUF_EMP_800MV_0DB_HSW,
-	DDI_BUF_EMP_800MV_3_5DB_HSW
-};
-
-static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-				    enum port port)
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+			     enum port port)
 {
 	uint32_t reg = DDI_BUF_CTL(port);
 	int i;
@@ -246,124 +234,6 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
  * DDI A (which is used for eDP)
  */
 
-void hsw_fdi_link_train(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	u32 temp, i, rx_ctl_val;
-
-	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
-	 * mode set "sequence for CRT port" document:
-	 * - TP1 to TP2 time with the default value
-	 * - FDI delay to 90h
-	 *
-	 * WaFDIAutoLinkSetTimingOverrride:hsw
-	 */
-	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
-				  FDI_RX_PWRDN_LANE0_VAL(2) |
-				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-
-	/* Enable the PCH Receiver FDI PLL */
-	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
-		     FDI_RX_PLL_ENABLE |
-		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
-	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-	POSTING_READ(_FDI_RXA_CTL);
-	udelay(220);
-
-	/* Switch from Rawclk to PCDclk */
-	rx_ctl_val |= FDI_PCDCLK;
-	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-
-	/* Configure Port Clock Select */
-	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
-
-	/* Start the training iterating through available voltages and emphasis,
-	 * testing each value twice. */
-	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
-		/* Configure DP_TP_CTL with auto-training */
-		I915_WRITE(DP_TP_CTL(PORT_E),
-					DP_TP_CTL_FDI_AUTOTRAIN |
-					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
-					DP_TP_CTL_LINK_TRAIN_PAT1 |
-					DP_TP_CTL_ENABLE);
-
-		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
-		 * DDI E does not support port reversal, the functionality is
-		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
-		 * port reversal bit */
-		I915_WRITE(DDI_BUF_CTL(PORT_E),
-			   DDI_BUF_CTL_ENABLE |
-			   ((intel_crtc->config.fdi_lanes - 1) << 1) |
-			   hsw_ddi_buf_ctl_values[i / 2]);
-		POSTING_READ(DDI_BUF_CTL(PORT_E));
-
-		udelay(600);
-
-		/* Program PCH FDI Receiver TU */
-		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
-
-		/* Enable PCH FDI Receiver with auto-training */
-		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
-		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-		POSTING_READ(_FDI_RXA_CTL);
-
-		/* Wait for FDI receiver lane calibration */
-		udelay(30);
-
-		/* Unset FDI_RX_MISC pwrdn lanes */
-		temp = I915_READ(_FDI_RXA_MISC);
-		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
-		I915_WRITE(_FDI_RXA_MISC, temp);
-		POSTING_READ(_FDI_RXA_MISC);
-
-		/* Wait for FDI auto training time */
-		udelay(5);
-
-		temp = I915_READ(DP_TP_STATUS(PORT_E));
-		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
-			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
-
-			/* Enable normal pixel sending for FDI */
-			I915_WRITE(DP_TP_CTL(PORT_E),
-				   DP_TP_CTL_FDI_AUTOTRAIN |
-				   DP_TP_CTL_LINK_TRAIN_NORMAL |
-				   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
-				   DP_TP_CTL_ENABLE);
-
-			return;
-		}
-
-		temp = I915_READ(DDI_BUF_CTL(PORT_E));
-		temp &= ~DDI_BUF_CTL_ENABLE;
-		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
-		POSTING_READ(DDI_BUF_CTL(PORT_E));
-
-		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
-		temp = I915_READ(DP_TP_CTL(PORT_E));
-		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
-		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		I915_WRITE(DP_TP_CTL(PORT_E), temp);
-		POSTING_READ(DP_TP_CTL(PORT_E));
-
-		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
-
-		rx_ctl_val &= ~FDI_RX_ENABLE;
-		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
-		POSTING_READ(_FDI_RXA_CTL);
-
-		/* Reset FDI_RX_MISC pwrdn lanes */
-		temp = I915_READ(_FDI_RXA_MISC);
-		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
-		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-		I915_WRITE(_FDI_RXA_MISC, temp);
-		POSTING_READ(_FDI_RXA_MISC);
-	}
-
-	DRM_ERROR("FDI link training failed!\n");
-}
-
 static struct intel_encoder *
 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 82ad84eefc8d..80b34ac31d0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3858,9 +3858,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->config.has_pch_encoder)
 		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 
-	if (intel_crtc->config.has_pch_encoder)
-		dev_priv->display.fdi_link_train(crtc);
-
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder);
@@ -11120,7 +11117,6 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.modeset_global_resources =
 				ivb_modeset_global_resources;
 		} else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
-			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 			dev_priv->display.write_eld = haswell_write_eld;
 			dev_priv->display.modeset_global_resources =
 				haswell_modeset_global_resources;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c093e71db7d..7f1d7f675953 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -668,11 +668,12 @@ void intel_crt_init(struct drm_device *dev);
 
 /* intel_ddi.c */
 void intel_prepare_ddi(struct drm_device *dev);
-void hsw_fdi_link_train(struct drm_crtc *crtc);
 void intel_ddi_init(struct drm_device *dev, enum port port);
 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
 			      enum port port);
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+			     enum port port);
 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 void intel_ddi_pll_init(struct drm_device *dev);
 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
-- 
1.8.1.4

[PATCH 47/66] drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable

[Daniel Vetter]

With this all the pch pre-enable work has been moved into the special
hsw crt encoder functions.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 4 ++++
 drivers/gpu/drm/i915/intel_display.c | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 2d8f4fe1b450..d3cae57d942a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -275,6 +275,10 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 static void hsw_crt_pre_enable(struct intel_encoder *encoder)
 {
+	struct drm_device *dev = encoder->base.dev;
+
+	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
+
 	hsw_fdi_link_train(encoder->base.crtc);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 80b34ac31d0a..43a40594841f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3855,8 +3855,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
-	if (intel_crtc->config.has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->pre_enable)
-- 
1.8.1.4

[PATCH 48/66] drm/i915: Move the SPLL enabling into hsw_crt_pre_enable

[Daniel Vetter]

The call to intel_ddi_pll_enable in haswell_crtc_mode_set is the only
function that still touches the hardware state from the crtc mode_set
callback on hsw. Since the SPLL isn't ever shared we can easily take
it out into the hsw crt encoder functions.

Temporarily we'll loose a bit of WARN_ON coverage with this, but once
the WRPLLs are switched over that will be restored. For the SPLL
selection add a WARN in the hsw fdi link training code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c |  8 ++++++++
 drivers/gpu/drm/i915/intel_ddi.c | 18 ------------------
 2 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d3cae57d942a..ec806e432545 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -187,6 +187,7 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
 
 	/* Configure Port Clock Select */
 	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
+	WARN_ON(intel_crtc->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
@@ -276,6 +277,13 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
 static void hsw_crt_pre_enable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
+	I915_WRITE(SPLL_CTL,
+		   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);
+	POSTING_READ(SPLL_CTL);
+	udelay(20);
 
 	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 13abde3e848f..4fde38a253f0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -718,23 +718,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 
 	switch (crtc->ddi_pll_sel) {
-	case PORT_CLK_SEL_LCPLL_2700:
-	case PORT_CLK_SEL_LCPLL_1350:
-	case PORT_CLK_SEL_LCPLL_810:
-		/*
-		 * LCPLL should always be enabled at this point of the mode set
-		 * sequence, so nothing to do.
-		 */
-		return;
-
-	case PORT_CLK_SEL_SPLL:
-		new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
-			  SPLL_PLL_SSC;
-		WARN(I915_READ(SPLL_CTL) & enable_bit, "SPLL already enabled\n");
-		I915_WRITE(SPLL_CTL, new_val);
-		POSTING_READ(SPLL_CTL);
-		udelay(20);
-		return;
 	case PORT_CLK_SEL_WRPLL1:
 	case PORT_CLK_SEL_WRPLL2:
 		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
@@ -759,7 +742,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 		WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
 		return;
 	default:
-		WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
 		return;
 	}
 
-- 
1.8.1.4

[PATCH 49/66] drm/i915: Move lpt_pch_enable int hsw_crt_enable

[Daniel Vetter]

Unfortunately this requires a bunch of exports for pch handling
functions, but there's been various plans floating around to extract
them all into an intel_pch.c helper library anyway.

In any case haswell_crtc_enable is now pch encoder free.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 147 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c | 160 ++---------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  14 +++
 3 files changed, 168 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index ec806e432545..9d7135b878c0 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -354,6 +354,150 @@ static void intel_enable_crt(struct intel_encoder *encoder)
 	intel_crt_set_dpms(encoder, crt->connector->base.dpms);
 }
 
+/* Program iCLKIP clock to the desired frequency */
+static void lpt_program_iclkip(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
+	u32 divsel, phaseinc, auxdiv, phasedir = 0;
+	u32 temp;
+
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* It is necessary to ungate the pixclk gate prior to programming
+	 * the divisors, and gate it back when it is done.
+	 */
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
+
+	/* Disable SSCCTL */
+	intel_sbi_write(dev_priv, SBI_SSCCTL6,
+			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
+				SBI_SSCCTL_DISABLE,
+			SBI_ICLK);
+
+	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
+	if (clock == 20000) {
+		auxdiv = 1;
+		divsel = 0x41;
+		phaseinc = 0x20;
+	} else {
+		/* The iCLK virtual clock root frequency is in MHz,
+		 * but the adjusted_mode->crtc_clock in in KHz. To get the
+		 * divisors, it is necessary to divide one by another, so we
+		 * convert the virtual clock precision to KHz here for higher
+		 * precision.
+		 */
+		u32 iclk_virtual_root_freq = 172800 * 1000;
+		u32 iclk_pi_range = 64;
+		u32 desired_divisor, msb_divisor_value, pi_value;
+
+		desired_divisor = (iclk_virtual_root_freq / clock);
+		msb_divisor_value = desired_divisor / iclk_pi_range;
+		pi_value = desired_divisor % iclk_pi_range;
+
+		auxdiv = 0;
+		divsel = msb_divisor_value - 2;
+		phaseinc = pi_value;
+	}
+
+	/* This should not happen with any sane values */
+	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
+	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
+		~SBI_SSCDIVINTPHASE_INCVAL_MASK);
+
+	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
+			clock,
+			auxdiv,
+			divsel,
+			phasedir,
+			phaseinc);
+
+	/* Program SSCDIVINTPHASE6 */
+	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
+	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
+	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
+
+	/* Program SSCAUXDIV */
+	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
+	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
+	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
+	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
+
+	/* Enable modulator and associated divider */
+	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+	temp &= ~SBI_SSCCTL_DISABLE;
+	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
+
+	/* Wait for initialization time */
+	udelay(24);
+
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
+static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
+				      enum transcoder cpu_transcoder)
+{
+	u32 val, pipeconf_val;
+
+	/* PCH only available on ILK+ */
+	BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
+
+	/* FDI must be feeding us bits for PCH ports */
+	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
+	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
+
+	/* Workaround: set timing override bit. */
+	val = I915_READ(_TRANSA_CHICKEN2);
+	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+	I915_WRITE(_TRANSA_CHICKEN2, val);
+
+	val = TRANS_ENABLE;
+	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
+
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+	    PIPECONF_INTERLACED_ILK)
+		val |= TRANS_INTERLACED;
+	else
+		val |= TRANS_PROGRESSIVE;
+
+	I915_WRITE(LPT_TRANSCONF, val);
+	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
+		DRM_ERROR("Failed to enable PCH transcoder\n");
+}
+
+static void lpt_pch_enable(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
+
+	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
+
+	lpt_program_iclkip(crtc);
+
+	/* Set transcoder timing. */
+	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
+
+	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
+}
+
+static void hsw_crt_enable(struct intel_encoder *encoder)
+{
+	lpt_pch_enable(encoder->base.crtc);
+
+	intel_enable_crt(encoder);
+}
+
 /* Special dpms function to support cloning between dvo/sdvo/crt. */
 static void intel_crt_dpms(struct drm_connector *connector, int mode)
 {
@@ -1006,16 +1150,17 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.compute_config = intel_crt_compute_config;
 	crt->base.disable = intel_disable_crt;
-	crt->base.enable = intel_enable_crt;
 	if (I915_HAS_HOTPLUG(dev))
 		crt->base.hpd_pin = HPD_CRT;
 	if (HAS_DDI(dev)) {
 		crt->base.get_config = hsw_crt_get_config;
 		crt->base.get_hw_state = hsw_crt_get_hw_state;
 		crt->base.pre_enable = hsw_crt_pre_enable;
+		crt->base.enable = hsw_crt_enable;
 	} else {
 		crt->base.get_config = intel_crt_get_config;
 		crt->base.get_hw_state = intel_crt_get_hw_state;
+		crt->base.enable = intel_enable_crt;
 	}
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_connector_unregister;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 43a40594841f..26b2eceb0d63 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -992,8 +992,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	     pll->name, state_string(state), state_string(cur_state));
 }
 
-static void assert_fdi_tx(struct drm_i915_private *dev_priv,
-			  enum pipe pipe, bool state)
+void assert_fdi_tx(struct drm_i915_private *dev_priv,
+		   enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
@@ -1015,11 +1015,9 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
-#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
-#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 
-static void assert_fdi_rx(struct drm_i915_private *dev_priv,
-			  enum pipe pipe, bool state)
+void assert_fdi_rx(struct drm_i915_private *dev_priv,
+		   enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
@@ -1032,8 +1030,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
-#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
-#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
@@ -1236,8 +1232,8 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 }
 
-static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
-					   enum pipe pipe)
+void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
+				    enum pipe pipe)
 {
 	int reg;
 	u32 val;
@@ -1692,37 +1688,6 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
 }
 
-static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
-				      enum transcoder cpu_transcoder)
-{
-	u32 val, pipeconf_val;
-
-	/* PCH only available on ILK+ */
-	BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
-
-	/* FDI must be feeding us bits for PCH ports */
-	assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
-	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
-
-	/* Workaround: set timing override bit. */
-	val = I915_READ(_TRANSA_CHICKEN2);
-	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
-	I915_WRITE(_TRANSA_CHICKEN2, val);
-
-	val = TRANS_ENABLE;
-	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
-
-	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
-	    PIPECONF_INTERLACED_ILK)
-		val |= TRANS_INTERLACED;
-	else
-		val |= TRANS_PROGRESSIVE;
-
-	I915_WRITE(LPT_TRANSCONF, val);
-	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
-		DRM_ERROR("Failed to enable PCH transcoder\n");
-}
-
 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 					    enum pipe pipe)
 {
@@ -3120,97 +3085,8 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 	mutex_unlock(&dev->struct_mutex);
 }
 
-/* Program iCLKIP clock to the desired frequency */
-static void lpt_program_iclkip(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
-	u32 divsel, phaseinc, auxdiv, phasedir = 0;
-	u32 temp;
-
-	mutex_lock(&dev_priv->dpio_lock);
-
-	/* It is necessary to ungate the pixclk gate prior to programming
-	 * the divisors, and gate it back when it is done.
-	 */
-	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
-
-	/* Disable SSCCTL */
-	intel_sbi_write(dev_priv, SBI_SSCCTL6,
-			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
-				SBI_SSCCTL_DISABLE,
-			SBI_ICLK);
-
-	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
-	if (clock == 20000) {
-		auxdiv = 1;
-		divsel = 0x41;
-		phaseinc = 0x20;
-	} else {
-		/* The iCLK virtual clock root frequency is in MHz,
-		 * but the adjusted_mode->crtc_clock in in KHz. To get the
-		 * divisors, it is necessary to divide one by another, so we
-		 * convert the virtual clock precision to KHz here for higher
-		 * precision.
-		 */
-		u32 iclk_virtual_root_freq = 172800 * 1000;
-		u32 iclk_pi_range = 64;
-		u32 desired_divisor, msb_divisor_value, pi_value;
-
-		desired_divisor = (iclk_virtual_root_freq / clock);
-		msb_divisor_value = desired_divisor / iclk_pi_range;
-		pi_value = desired_divisor % iclk_pi_range;
-
-		auxdiv = 0;
-		divsel = msb_divisor_value - 2;
-		phaseinc = pi_value;
-	}
-
-	/* This should not happen with any sane values */
-	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
-		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
-	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
-		~SBI_SSCDIVINTPHASE_INCVAL_MASK);
-
-	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-			clock,
-			auxdiv,
-			divsel,
-			phasedir,
-			phaseinc);
-
-	/* Program SSCDIVINTPHASE6 */
-	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
-	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
-	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
-	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
-	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
-	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
-
-	/* Program SSCAUXDIV */
-	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
-	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
-	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
-	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
-
-	/* Enable modulator and associated divider */
-	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
-	temp &= ~SBI_SSCCTL_DISABLE;
-	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
-
-	/* Wait for initialization time */
-	udelay(24);
-
-	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
-
-	mutex_unlock(&dev_priv->dpio_lock);
-}
-
-static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
-						enum pipe pch_transcoder)
+void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
+					 enum pipe pch_transcoder)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3373,23 +3249,6 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
-static void lpt_pch_enable(struct drm_crtc *crtc)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
-
-	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
-
-	lpt_program_iclkip(crtc);
-
-	/* Set transcoder timing. */
-	ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
-
-	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
-}
-
 static void intel_put_shared_dpll(struct intel_crtc *crtc)
 {
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
@@ -3876,9 +3735,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_update_watermarks(crtc);
 	intel_enable_pipe(intel_crtc);
 
-	if (intel_crtc->config.has_pch_encoder)
-		lpt_pch_enable(crtc);
-
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
 		encoder->enable(encoder);
 		intel_opregion_notify_encoder(encoder, true);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7f1d7f675953..5b8e34c6907e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -782,6 +782,20 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_config *pipe_config);
 int intel_format_to_fourcc(int format);
 
+/* pch handling code shared with intel_crt on hsw/lpt */
+void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
+					 enum pipe pch_transcoder);
+void assert_fdi_tx(struct drm_i915_private *dev_priv,
+		   enum pipe pipe, bool state);
+#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
+#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
+void assert_fdi_rx(struct drm_i915_private *dev_priv,
+		   enum pipe pipe, bool state);
+#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
+#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
+void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
+				    enum pipe pipe);
+
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
-- 
1.8.1.4

[PATCH 50/66] drm/i915: Move the pch fifo underrun handling into hsw_crt_disable

[Daniel Vetter]

Yet another pch encoder special case quenched from haswell modeset
code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 11 ++++++++++-
 drivers/gpu/drm/i915/intel_display.c |  2 --
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 9d7135b878c0..0e109325cbcb 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -347,6 +347,14 @@ static void intel_disable_crt(struct intel_encoder *encoder)
 	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 }
 
+static void hsw_crt_disable(struct intel_encoder *encoder)
+{
+	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+	intel_set_pch_fifo_underrun_reporting(encoder->base.dev,
+					      TRANSCODER_A, false);
+}
+
 static void intel_enable_crt(struct intel_encoder *encoder)
 {
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -1149,7 +1157,6 @@ void intel_crt_init(struct drm_device *dev)
 		crt->adpa_reg = ADPA;
 
 	crt->base.compute_config = intel_crt_compute_config;
-	crt->base.disable = intel_disable_crt;
 	if (I915_HAS_HOTPLUG(dev))
 		crt->base.hpd_pin = HPD_CRT;
 	if (HAS_DDI(dev)) {
@@ -1157,10 +1164,12 @@ void intel_crt_init(struct drm_device *dev)
 		crt->base.get_hw_state = hsw_crt_get_hw_state;
 		crt->base.pre_enable = hsw_crt_pre_enable;
 		crt->base.enable = hsw_crt_enable;
+		crt->base.disable = hsw_crt_disable;
 	} else {
 		crt->base.get_config = intel_crt_get_config;
 		crt->base.get_hw_state = intel_crt_get_hw_state;
 		crt->base.enable = intel_enable_crt;
+		crt->base.disable = intel_disable_crt;
 	}
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_connector_unregister;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 26b2eceb0d63..84f5cbd3863c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3844,8 +3844,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 		encoder->disable(encoder);
 	}
 
-	if (intel_crtc->config.has_pch_encoder)
-		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
 	intel_disable_pipe(dev_priv, pipe);
 
 	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
-- 
1.8.1.4

[PATCH 51/66] drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder

[Daniel Vetter]

We can just create a ->post_disable hook to shovel all the fdi/pch
specific code into it - it's all only used by the crt encoder anyway.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 18 ------------------
 2 files changed, 26 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 0e109325cbcb..208f54f28d08 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -355,6 +355,31 @@ static void hsw_crt_disable(struct intel_encoder *encoder)
 					      TRANSCODER_A, false);
 }
 
+static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(LPT_TRANSCONF);
+	val &= ~TRANS_ENABLE;
+	I915_WRITE(LPT_TRANSCONF, val);
+	/* wait for PCH transcoder off, transcoder state */
+	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
+		DRM_ERROR("Failed to disable PCH transcoder\n");
+
+	/* Workaround: clear timing override bit. */
+	val = I915_READ(_TRANSA_CHICKEN2);
+	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+	I915_WRITE(_TRANSA_CHICKEN2, val);
+}
+
+static void hsw_crt_post_disable(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	lpt_disable_pch_transcoder(dev_priv);
+}
+
 static void intel_enable_crt(struct intel_encoder *encoder)
 {
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -1165,6 +1190,7 @@ void intel_crt_init(struct drm_device *dev)
 		crt->base.pre_enable = hsw_crt_pre_enable;
 		crt->base.enable = hsw_crt_enable;
 		crt->base.disable = hsw_crt_disable;
+		crt->base.post_disable = hsw_crt_post_disable;
 	} else {
 		crt->base.get_config = intel_crt_get_config;
 		crt->base.get_hw_state = intel_crt_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84f5cbd3863c..0e2c9f242b4d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1718,23 +1718,6 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	val = I915_READ(LPT_TRANSCONF);
-	val &= ~TRANS_ENABLE;
-	I915_WRITE(LPT_TRANSCONF, val);
-	/* wait for PCH transcoder off, transcoder state */
-	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
-		DRM_ERROR("Failed to disable PCH transcoder\n");
-
-	/* Workaround: clear timing override bit. */
-	val = I915_READ(_TRANSA_CHICKEN2);
-	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-	I915_WRITE(_TRANSA_CHICKEN2, val);
-}
-
 /**
  * intel_enable_pipe - enable a pipe, asserting requirements
  * @crtc: crtc responsible for the pipe
@@ -3857,7 +3840,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (intel_crtc->config.has_pch_encoder) {
-		lpt_disable_pch_transcoder(dev_priv);
 		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 		intel_ddi_fdi_disable(crtc);
 	}
-- 
1.8.1.4

[PATCH 52/66] drm/i915: Move pch fifo underrun report re-enabling into hsw_crt_post_disable

[Daniel Vetter]

Step 2 in pimping the hsw_crt_post_disable hook.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 208f54f28d08..7a146f6d8c39 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -378,6 +378,8 @@ static void hsw_crt_post_disable(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	lpt_disable_pch_transcoder(dev_priv);
+
+	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 }
 
 static void intel_enable_crt(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0e2c9f242b4d..b370817f787f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3840,7 +3840,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (intel_crtc->config.has_pch_encoder) {
-		intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 		intel_ddi_fdi_disable(crtc);
 	}
 
-- 
1.8.1.4

[PATCH 53/66] drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable

[Daniel Vetter]

With this all the pch encoder specific code is now gone from the
haswell ->crtc_disable function. Which finally readies the stage
for the last piece of all the hsw crt encoder rework, namely also
moving the SPLL disabling into the encoder post_disable function.
Which the next patch will do.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     | 28 +---------------------------
 drivers/gpu/drm/i915/intel_display.c |  4 ----
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 4 files changed, 29 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 7a146f6d8c39..fd465bf7fd0d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -372,6 +372,31 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 	I915_WRITE(_TRANSA_CHICKEN2, val);
 }
 
+static void hsw_fdi_disable(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	uint32_t val;
+
+	intel_ddi_post_disable(encoder);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_RX_ENABLE;
+	I915_WRITE(_FDI_RXA_CTL, val);
+
+	val = I915_READ(_FDI_RXA_MISC);
+	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
+	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
+	I915_WRITE(_FDI_RXA_MISC, val);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_PCDCLK;
+	I915_WRITE(_FDI_RXA_CTL, val);
+
+	val = I915_READ(_FDI_RXA_CTL);
+	val &= ~FDI_RX_PLL_ENABLE;
+	I915_WRITE(_FDI_RXA_CTL, val);
+}
+
 static void hsw_crt_post_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
@@ -380,6 +405,8 @@ static void hsw_crt_post_disable(struct intel_encoder *encoder)
 	lpt_disable_pch_transcoder(dev_priv);
 
 	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
+
+	hsw_fdi_disable(encoder);
 }
 
 static void intel_enable_crt(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4fde38a253f0..9d455967e27b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1131,7 +1131,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 	}
 }
 
-static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
+void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
@@ -1317,32 +1317,6 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
 	udelay(600);
 }
 
-void intel_ddi_fdi_disable(struct drm_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
-	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
-	uint32_t val;
-
-	intel_ddi_post_disable(intel_encoder);
-
-	val = I915_READ(_FDI_RXA_CTL);
-	val &= ~FDI_RX_ENABLE;
-	I915_WRITE(_FDI_RXA_CTL, val);
-
-	val = I915_READ(_FDI_RXA_MISC);
-	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
-	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
-	I915_WRITE(_FDI_RXA_MISC, val);
-
-	val = I915_READ(_FDI_RXA_CTL);
-	val &= ~FDI_PCDCLK;
-	I915_WRITE(_FDI_RXA_CTL, val);
-
-	val = I915_READ(_FDI_RXA_CTL);
-	val &= ~FDI_RX_PLL_ENABLE;
-	I915_WRITE(_FDI_RXA_CTL, val);
-}
-
 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b370817f787f..728b5a25cb80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3839,10 +3839,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
-	if (intel_crtc->config.has_pch_encoder) {
-		intel_ddi_fdi_disable(crtc);
-	}
-
 	intel_crtc->active = false;
 	intel_update_watermarks(crtc);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b8e34c6907e..77414333804a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -687,7 +687,7 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc);
 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-void intel_ddi_fdi_disable(struct drm_crtc *crtc);
+void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
 void intel_ddi_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_config *pipe_config);
 
-- 
1.8.1.4

[PATCH 54/66] drm/i915: Move SPLL disabling into hsw_crt_post_disable

[Daniel Vetter]

Similar to how the ->crtc_mode_set hook should touch the hardware to
enable anything the ->crtc_off hook should disable anything in the
hardware. Otherwise runtime pm for dpms will not work.

Currently the only things left int the haswell_crtc_off hook is
disabling the ddi plls. We can't move the WRPLL enabling out yet
because the current ddi pll sharing code used by the haswell code
doesn't separately track active users and overall users. This must be
fixed by porting it to the generic shared display pll framework, which
is powerful enough.

But the SPLL source is only used by the crt encoder and so can be
moved already. We only need to make sure that the ddi port E is
already off, which hsw_fdi_disable does by calling
intel_ddi_post_disable.

With this the code reorg to shuffle hsw fdi/lpt specific code into a
new hsw-specific crt encoder type is now finally complete.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c | 7 +++++++
 drivers/gpu/drm/i915/intel_ddi.c | 7 -------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index fd465bf7fd0d..c4b1b1f82d01 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -401,12 +401,19 @@ static void hsw_crt_post_disable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t val;
 
 	lpt_disable_pch_transcoder(dev_priv);
 
 	intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 
 	hsw_fdi_disable(encoder);
+
+	DRM_DEBUG_KMS("Disabling SPLL\n");
+	val = I915_READ(SPLL_CTL);
+	WARN_ON(!(val & SPLL_PLL_ENABLE));
+	I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
+	POSTING_READ(SPLL_CTL);
 }
 
 static void intel_enable_crt(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9d455967e27b..534cdb42e788 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -263,13 +263,6 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 	uint32_t val;
 
 	switch (intel_crtc->ddi_pll_sel) {
-	case PORT_CLK_SEL_SPLL:
-		DRM_DEBUG_KMS("Disabling SPLL\n");
-		val = I915_READ(SPLL_CTL);
-		WARN_ON(!(val & SPLL_PLL_ENABLE));
-		I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
-		POSTING_READ(SPLL_CTL);
-		break;
 	case PORT_CLK_SEL_WRPLL1:
 		plls->wrpll1_refcount--;
 		if (plls->wrpll1_refcount == 0) {
-- 
1.8.1.4

[PATCH 55/66] drm/i915: Add a debugfs file for the shared dpll state

[Daniel Vetter]

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1e83ae45041c..c99951fdc572 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2370,6 +2370,31 @@ static int i915_display_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_shared_dplls_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int i;
+
+	drm_modeset_lock_all(dev);
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+
+		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
+		seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
+			   pll->active, yesno(pll->on));
+		seq_printf(m, " tracked hardware state:\n");
+		seq_printf(m, " dpll:    0x%08x\n", pll->hw_state.dpll);
+		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
+		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);
+		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);
+	}
+	drm_modeset_unlock_all(dev);
+
+	return 0;
+}
+
 struct pipe_crc_info {
 	const char *name;
 	struct drm_device *dev;
@@ -3811,6 +3836,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_pc8_status", i915_pc8_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
 	{"i915_display_info", i915_display_info, 0},
+	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
 
-- 
1.8.1.4

[PATCH 56/66] drm/i915: Move ddi_pll_sel into the pipe config

[Daniel Vetter]

Just boring sed job for preparation.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c |  4 ++--
 drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h |  5 +++--
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c4b1b1f82d01..beffae116f05 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -186,8 +186,8 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 
 	/* Configure Port Clock Select */
-	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
-	WARN_ON(intel_crtc->ddi_pll_sel != PORT_CLK_SEL_SPLL);
+	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
+	WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 534cdb42e788..2adcc917806e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -262,7 +262,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t val;
 
-	switch (intel_crtc->ddi_pll_sel) {
+	switch (intel_crtc->config.ddi_pll_sel) {
 	case PORT_CLK_SEL_WRPLL1:
 		plls->wrpll1_refcount--;
 		if (plls->wrpll1_refcount == 0) {
@@ -288,7 +288,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 
-	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
+	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 }
 
 #define LC_FREQ 2700
@@ -623,13 +623,13 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 
 		switch (intel_dp->link_bw) {
 		case DP_LINK_BW_1_62:
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 			break;
 		case DP_LINK_BW_2_7:
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 			break;
 		case DP_LINK_BW_5_4:
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 			break;
 		default:
 			DRM_ERROR("Link bandwidth %d unsupported\n",
@@ -673,16 +673,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 
 		if (reg == WRPLL_CTL1) {
 			plls->wrpll1_refcount++;
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 		} else {
 			plls->wrpll2_refcount++;
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 		}
 
 	} else if (type == INTEL_OUTPUT_ANALOG) {
 		DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 			      pipe_name(pipe));
-		intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
+		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
 	} else {
 		WARN(1, "Invalid DDI encoder type %d\n", type);
 		return false;
@@ -710,10 +710,10 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
 	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 
-	switch (crtc->ddi_pll_sel) {
+	switch (crtc->config.ddi_pll_sel) {
 	case PORT_CLK_SEL_WRPLL1:
 	case PORT_CLK_SEL_WRPLL2:
-		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
+		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
 			pll_name = "WRPLL1";
 			reg = WRPLL_CTL1;
 			refcount = plls->wrpll1_refcount;
@@ -1035,14 +1035,14 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
 			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 
 		if (!intel_crtc->active) {
-			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
+			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 			continue;
 		}
 
-		intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
+		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
 								 pipe);
 
-		switch (intel_crtc->ddi_pll_sel) {
+		switch (intel_crtc->config.ddi_pll_sel) {
 		case PORT_CLK_SEL_WRPLL1:
 			dev_priv->ddi_plls.wrpll1_refcount++;
 			break;
@@ -1098,8 +1098,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 		intel_edp_panel_on(intel_dp);
 	}
 
-	WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
-	I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
+	WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
+	I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
 
 	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 77414333804a..e1d079fe47ea 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -307,6 +307,9 @@ struct intel_crtc_config {
 	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
 	enum intel_dpll_id shared_dpll;
 
+	/* PORT_CLK_SEL for DDI ports. */
+	uint32_t ddi_pll_sel;
+
 	/* Actual register state of the dpll, for shared dpll cross-checking. */
 	struct intel_dpll_hw_state dpll_hw_state;
 
@@ -393,8 +396,6 @@ struct intel_crtc {
 	struct intel_crtc_config *new_config;
 	bool new_enabled;
 
-	uint32_t ddi_pll_sel;
-
 	/* reset counter value when the last flip was submitted */
 	unsigned int reset_counter;
 
-- 
1.8.1.4

[PATCH 57/66] drm/i915: State readout and cross-checking for ddi_pll_sel

[Daniel Vetter]

To make things a bit more manageable extract a new function for
reading out common ddi port state. This means a bit of duplication
between encoders and the core since both look at the same registers,
but doesn't seem worth to make a fuzz about.

We can also remove the state readout code in intel_ddi_setup_hw_pll_state.
That code is only called from the hardware take over and not the cross
check code, and only after the crtc state is reconstructed. So we can
rely on an accurate value of crtc->config.ddi_pll_sel already.

Compared to the old code also trust the hw state more and don't
special-case port A - we want to cross-check the actual-state, not
bake in our own assumptions about how this is supposed to all be
linked up.

v2: Make use of the read-out ddi_pll_sel in intel_ddi_clock_get.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_ddi.c     | 40 +-----------------------------
 drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++++++------------
 3 files changed, 34 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64d40f22e708..4c1cefb5f3eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,7 @@ enum punit_power_well {
 #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
 #define  TRANS_DDI_PORT_MASK		(7<<28)
+#define  TRANS_DDI_PORT_SHIFT		28
 #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
 #define  TRANS_DDI_PORT_NONE		(0<<28)
 #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2adcc917806e..571cfe431558 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -481,11 +481,10 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 				struct intel_crtc_config *pipe_config)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	enum port port = intel_ddi_get_encoder_port(encoder);
 	int link_clock = 0;
 	u32 val, pll;
 
-	val = I915_READ(PORT_CLK_SEL(port));
+	val = pipe_config->ddi_pll_sel;
 	switch (val & PORT_CLK_SEL_MASK) {
 	case PORT_CLK_SEL_LCPLL_810:
 		link_clock = 81000;
@@ -987,40 +986,6 @@ static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	return intel_ddi_get_port_state(encoder, pipe, port);
 }
 
-static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
-				       enum pipe pipe)
-{
-	uint32_t temp, ret;
-	enum port port = I915_MAX_PORTS;
-	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
-								      pipe);
-	int i;
-
-	if (cpu_transcoder == TRANSCODER_EDP) {
-		port = PORT_A;
-	} else {
-		temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
-		temp &= TRANS_DDI_PORT_MASK;
-
-		for (i = PORT_B; i <= PORT_E; i++)
-			if (temp == TRANS_DDI_SELECT_PORT(i))
-				port = i;
-	}
-
-	if (port == I915_MAX_PORTS) {
-		WARN(1, "Pipe %c enabled on an unknown port\n",
-		     pipe_name(pipe));
-		ret = PORT_CLK_SEL_NONE;
-	} else {
-		ret = I915_READ(PORT_CLK_SEL(port));
-		DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
-			      "0x%08x\n", pipe_name(pipe), port_name(port),
-			      ret);
-	}
-
-	return ret;
-}
-
 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1039,9 +1004,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
 			continue;
 		}
 
-		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
-								 pipe);
-
 		switch (intel_crtc->config.ddi_pll_sel) {
 		case PORT_CLK_SEL_WRPLL1:
 			dev_priv->ddi_plls.wrpll1_refcount++;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 728b5a25cb80..1601da1b57a1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7006,6 +7006,35 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	return 0;
 }
 
+static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
+				       struct intel_crtc_config *pipe_config)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum port port;
+	uint32_t tmp;
+
+	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
+
+	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+
+	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
+	/*
+	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
+	 * DDI E. So just check whether this pipe is wired to DDI E and whether
+	 * the PCH transcoder is on.
+	 */
+	if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
+		pipe_config->has_pch_encoder = true;
+
+		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
+		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+		ironlake_get_fdi_m_n_config(crtc, pipe_config);
+	}
+}
+
 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 				    struct intel_crtc_config *pipe_config)
 {
@@ -7051,22 +7080,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	if (!(tmp & PIPECONF_ENABLE))
 		return false;
 
-	/*
-	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
-	 * DDI E. So just check whether this pipe is wired to DDI E and whether
-	 * the PCH transcoder is on.
-	 */
-	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
-	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
-	    I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
-		pipe_config->has_pch_encoder = true;
-
-		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
-		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
-					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
-		ironlake_get_fdi_m_n_config(crtc, pipe_config);
-	}
+	haswell_get_ddi_port_state(crtc, pipe_config);
 
 	intel_get_pipe_timings(crtc, pipe_config);
 
@@ -9521,6 +9535,8 @@ intel_pipe_config_compare(struct drm_device *dev,
 
 	PIPE_CONF_CHECK_I(double_wide);
 
+	PIPE_CONF_CHECK_X(ddi_pll_sel);
+
 	PIPE_CONF_CHECK_I(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
-- 
1.8.1.4

[PATCH 58/66] drm/i915: Precompute static ddi_pll_sel values in encoders

[Daniel Vetter]

This way only the dynamic WRPLL selection for hdmi ddi mode is
done in intel_ddi_pll_select.

v2: Don't clobber the precomputed values when selecting clocks fro
hdmi encoders.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c |  4 +++-
 drivers/gpu/drm/i915/intel_ddi.c | 34 +++-------------------------------
 drivers/gpu/drm/i915/intel_dp.c  | 23 ++++++++++++++++++++---
 3 files changed, 26 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index beffae116f05..71592993520d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -655,8 +655,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
 		pipe_config->pipe_bpp = 24;
 
 	/* FDI must always be 2.7 GHz */
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev)) {
+		pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 		pipe_config->port_clock = 135000 * 2;
+	}
 
 	return true;
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 571cfe431558..cc03f0af517b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 			POSTING_READ(WRPLL_CTL1);
 		}
+		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 		break;
 	case PORT_CLK_SEL_WRPLL2:
 		plls->wrpll2_refcount--;
@@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 			POSTING_READ(WRPLL_CTL2);
 		}
+		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 		break;
 	}
 
 	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
-
-	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 }
 
 #define LC_FREQ 2700
@@ -608,7 +608,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
-	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 	int type = intel_encoder->type;
@@ -617,26 +616,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 
 	intel_ddi_put_crtc_pll(crtc);
 
-	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
-			break;
-		case DP_LINK_BW_2_7:
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
-			break;
-		case DP_LINK_BW_5_4:
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
-			break;
-		default:
-			DRM_ERROR("Link bandwidth %d unsupported\n",
-				  intel_dp->link_bw);
-			return false;
-		}
-
-	} else if (type == INTEL_OUTPUT_HDMI) {
+	if (type == INTEL_OUTPUT_HDMI) {
 		uint32_t reg, val;
 		unsigned p, n2, r2;
 
@@ -677,14 +657,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 			plls->wrpll2_refcount++;
 			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 		}
-
-	} else if (type == INTEL_OUTPUT_ANALOG) {
-		DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
-			      pipe_name(pipe));
-		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
-	} else {
-		WARN(1, "Invalid DDI encoder type %d\n", type);
-		return false;
 	}
 
 	return true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ca94be9554f4..340fdd2be3ba 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -707,6 +707,22 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
 }
 
 static void
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
+{
+	switch (link_bw) {
+	case DP_LINK_BW_1_62:
+		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+		break;
+	case DP_LINK_BW_2_7:
+		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+		break;
+	case DP_LINK_BW_5_4:
+		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+		break;
+	}
+}
+
+static void
 intel_dp_set_clock(struct intel_encoder *encoder,
 		   struct intel_crtc_config *pipe_config, int link_bw)
 {
@@ -717,8 +733,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	if (IS_G4X(dev)) {
 		divisor = gen4_dpll;
 		count = ARRAY_SIZE(gen4_dpll);
-	} else if (IS_HASWELL(dev)) {
-		/* Haswell has special-purpose DP DDI clocks. */
 	} else if (HAS_PCH_SPLIT(dev)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
@@ -865,7 +879,10 @@ found:
 				&pipe_config->dp_m2_n2);
 	}
 
-	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
+	if (IS_HASWELL(dev))
+		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
+	else
+		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 
 	return true;
 }
-- 
1.8.1.4

[PATCH 59/66] drm/i915: Basic shared dpll support for WRPLLs

[Daniel Vetter]

Just filing in names and ids, but not yet officially registering them
so that the hw state cross checker doesn't completely freak out about
them. Still since we do already read out and cross check
config->shared_dpll the basics are now there to flesh out the wrpll
shared dpll implementation.

The idea is now to roll out all the callbacks step-by-step and then at
the end switch to the shared dpll framework. This way hw and sw
changes are clearly separated.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |  6 ++++--
 drivers/gpu/drm/i915/intel_ddi.c     | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++--------
 3 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6eac92e0a22..babeb7e92ee4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -176,8 +176,10 @@ struct drm_i915_private;
 enum intel_dpll_id {
 	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 	/* real shared dpll ids must be >= 0 */
-	DPLL_ID_PCH_PLL_A,
-	DPLL_ID_PCH_PLL_B,
+	DPLL_ID_PCH_PLL_A = 0,
+	DPLL_ID_PCH_PLL_B = 1,
+	DPLL_ID_WRPLL1 = 0,
+	DPLL_ID_WRPLL2 = 1,
 };
 #define I915_NUM_PLLS 2
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cc03f0af517b..8316e0e624a4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -653,9 +653,11 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 		if (reg == WRPLL_CTL1) {
 			plls->wrpll1_refcount++;
 			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
+			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
 		} else {
 			plls->wrpll2_refcount++;
 			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
+			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
 		}
 	}
 
@@ -1183,10 +1185,25 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 	}
 }
 
+static char *hsw_ddi_pll_names[] = {
+	"WRPLL 1",
+	"WRPLL 2",
+};
+
 void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t val = I915_READ(LCPLL_CTL);
+	int i;
+
+	/* Dummy setup until everything is moved over to avoid upsetting the hw
+	 * state cross checker. */
+	dev_priv->num_shared_dpll = 0;
+
+	for (i = 0; i < 2; i++) {
+		dev_priv->shared_dplls[i].id = i;
+		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
+	}
 
 	/* The LCPLL register should be turned on by the BIOS. For now let's
 	 * just check its state and print errors in case something is wrong.
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1601da1b57a1..fc7cd89b8921 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7019,6 +7019,16 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
 	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
+
+	switch (pipe_config->ddi_pll_sel) {
+	case PORT_CLK_SEL_WRPLL1:
+		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
+		break;
+	case PORT_CLK_SEL_WRPLL2:
+		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
+		break;
+	}
+
 	/*
 	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
 	 * DDI E. So just check whether this pipe is wired to DDI E and whether
@@ -10340,12 +10350,6 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
 	.page_flip = intel_crtc_page_flip,
 };
 
-static void intel_cpu_pll_init(struct drm_device *dev)
-{
-	if (HAS_DDI(dev))
-		intel_ddi_pll_init(dev);
-}
-
 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *hw_state)
@@ -10433,7 +10437,9 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	if (HAS_DDI(dev))
+		intel_ddi_pll_init(dev);
+	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 		ibx_pch_dpll_init(dev);
 	else
 		dev_priv->num_shared_dpll = 0;
@@ -11232,7 +11238,6 @@ void intel_modeset_init(struct drm_device *dev)
 	intel_init_dpio(dev);
 	intel_reset_dpio(dev);
 
-	intel_cpu_pll_init(dev);
 	intel_shared_dpll_init(dev);
 
 	/* Just disable it once at startup */
-- 
1.8.1.4

[PATCH 60/66] drm/i915: Document that the pll->mode_set hook is optional

[Daniel Vetter]

The WRPLLs won't use them.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index babeb7e92ee4..b01ee265310f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -198,6 +198,8 @@ struct intel_shared_dpll {
 	/* should match the index in the dev_priv->shared_dplls array */
 	enum intel_dpll_id id;
 	struct intel_dpll_hw_state hw_state;
+	/* The mode_set hook is optional and should be used together with the
+	 * intel_prepare_shared_dpll function. */
 	void (*mode_set)(struct drm_i915_private *dev_priv,
 			 struct intel_shared_dpll *pll);
 	void (*enable)(struct drm_i915_private *dev_priv,
-- 
1.8.1.4

[PATCH 61/66] drm/i915: State readout support for WRPLLs

[Daniel Vetter]

Still tacked onto the side, but slowly getting there.

v2: Don't forget the debugfs file.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  1 +
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_ddi.c     | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  9 +++++++++
 5 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c99951fdc572..a579685348aa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2389,6 +2389,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
 		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);
 		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);
+		seq_printf(m, " wrpll:   0x%08x\n", pll->hw_state.wrpll);
 	}
 	drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b01ee265310f..bebc507f776b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -188,6 +188,7 @@ struct intel_dpll_hw_state {
 	uint32_t dpll_md;
 	uint32_t fp0;
 	uint32_t fp1;
+	uint32_t wrpll;
 };
 
 struct intel_shared_dpll {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c1cefb5f3eb..99051e6348b8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5505,6 +5505,7 @@ enum punit_power_well {
 /* WRPLL */
 #define WRPLL_CTL1			0x46040
 #define WRPLL_CTL2			0x46060
+#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE		(1<<31)
 #define  WRPLL_PLL_SSC			(1<<28)
 #define  WRPLL_PLL_NON_SSC		(2<<28)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8316e0e624a4..73875ee4bb68 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -659,6 +659,8 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
 		}
+
+		intel_crtc->config.dpll_hw_state.wrpll = val;
 	}
 
 	return true;
@@ -1185,6 +1187,18 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 	}
 }
 
+static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
+				     struct intel_shared_dpll *pll,
+				     struct intel_dpll_hw_state *hw_state)
+{
+	uint32_t val;
+
+	val = I915_READ(WRPLL_CTL(pll->id));
+	hw_state->wrpll = val;
+
+	return val & WRPLL_PLL_ENABLE;
+}
+
 static char *hsw_ddi_pll_names[] = {
 	"WRPLL 1",
 	"WRPLL 2",
@@ -1203,6 +1217,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	for (i = 0; i < 2; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
+		dev_priv->shared_dplls[i].get_hw_state =
+			hsw_ddi_pll_get_hw_state;
 	}
 
 	/* The LCPLL register should be turned on by the BIOS. For now let's
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc7cd89b8921..b5086fd83596 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7011,6 +7011,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_shared_dpll *pll;
 	enum port port;
 	uint32_t tmp;
 
@@ -7029,6 +7030,13 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 		break;
 	}
 
+	if (pipe_config->shared_dpll >= 0) {
+		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
+
+		WARN_ON(!pll->get_hw_state(dev_priv, pll,
+					   &pipe_config->dpll_hw_state));
+	}
+
 	/*
 	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
 	 * DDI E. So just check whether this pipe is wired to DDI E and whether
@@ -9552,6 +9560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
 	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
 	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
 
 	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
-- 
1.8.1.4

[PATCH 62/66] drm/i915: ->disable hook for WRPLLs

[Daniel Vetter]

Currently still with a redudant WARN_ON in there, the common shared
dpll code will take care of this in the future.

Also we need to flip the switch for the transitional hack now to make
sure that we disable the right pll.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 27 ++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_display.c |  8 +++++---
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 73875ee4bb68..e7e1a84fe453 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -260,28 +260,21 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	uint32_t val;
+
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(intel_crtc);
 
 	switch (intel_crtc->config.ddi_pll_sel) {
 	case PORT_CLK_SEL_WRPLL1:
 		plls->wrpll1_refcount--;
 		if (plls->wrpll1_refcount == 0) {
-			DRM_DEBUG_KMS("Disabling WRPLL 1\n");
-			val = I915_READ(WRPLL_CTL1);
-			WARN_ON(!(val & WRPLL_PLL_ENABLE));
-			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
-			POSTING_READ(WRPLL_CTL1);
+			pll->disable(dev_priv, pll);
 		}
 		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 		break;
 	case PORT_CLK_SEL_WRPLL2:
 		plls->wrpll2_refcount--;
 		if (plls->wrpll2_refcount == 0) {
-			DRM_DEBUG_KMS("Disabling WRPLL 2\n");
-			val = I915_READ(WRPLL_CTL2);
-			WARN_ON(!(val & WRPLL_PLL_ENABLE));
-			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
-			POSTING_READ(WRPLL_CTL2);
+			pll->disable(dev_priv, pll);
 		}
 		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 		break;
@@ -1187,6 +1180,17 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
+				struct intel_shared_dpll *pll)
+{
+	uint32_t val;
+
+	val = I915_READ(WRPLL_CTL(pll->id));
+	WARN_ON(!(val & WRPLL_PLL_ENABLE));
+	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
+	POSTING_READ(WRPLL_CTL(pll->id));
+}
+
 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *hw_state)
@@ -1217,6 +1221,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	for (i = 0; i < 2; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
+		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
 		dev_priv->shared_dplls[i].get_hw_state =
 			hsw_ddi_pll_get_hw_state;
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5086fd83596..b890c97f1312 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4788,9 +4788,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	if (HAS_IPS(dev))
 		hsw_compute_ips_config(crtc, pipe_config);
 
-	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
-	 * clock survives for now. */
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	/*
+	 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
+	 * old clock survives for now.
+	 */
+	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
 		pipe_config->shared_dpll = crtc->config.shared_dpll;
 
 	if (pipe_config->has_pch_encoder)
-- 
1.8.1.4

[PATCH 63/66] drm/i915: ->enable hook for WRPLLs

[Daniel Vetter]

This time around another cute hack to pre-fill the pll->hw_state with
the right values. And also remove a bunch of checks which will be
replaced by lots more checks in the common framework.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c | 51 +++++++++++++++-------------------------
 1 file changed, 19 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e7e1a84fe453..21e451ea0c69 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -610,6 +610,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 	intel_ddi_put_crtc_pll(crtc);
 
 	if (type == INTEL_OUTPUT_HDMI) {
+		struct intel_shared_dpll *pll;
 		uint32_t reg, val;
 		unsigned p, n2, r2;
 
@@ -654,6 +655,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 		}
 
 		intel_crtc->config.dpll_hw_state.wrpll = val;
+
+		pll = &dev_priv->shared_dplls[intel_crtc->config.shared_dpll];
+		pll->hw_state.wrpll = val;
 	}
 
 	return true;
@@ -668,54 +672,24 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
-	int clock = crtc->config.port_clock;
-	uint32_t reg, cur_val, new_val;
 	int refcount;
-	const char *pll_name;
-	uint32_t enable_bit = (1 << 31);
-	unsigned int p, n2, r2;
-
-	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
-	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
+	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
 	switch (crtc->config.ddi_pll_sel) {
 	case PORT_CLK_SEL_WRPLL1:
 	case PORT_CLK_SEL_WRPLL2:
 		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
-			pll_name = "WRPLL1";
-			reg = WRPLL_CTL1;
 			refcount = plls->wrpll1_refcount;
 		} else {
-			pll_name = "WRPLL2";
-			reg = WRPLL_CTL2;
 			refcount = plls->wrpll2_refcount;
 		}
-
-		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
-
-		new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
-			  WRPLL_DIVIDER_REFERENCE(r2) |
-			  WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
-
 		break;
-
-	case PORT_CLK_SEL_NONE:
-		WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
-		return;
 	default:
 		return;
 	}
 
-	cur_val = I915_READ(reg);
-
-	WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
 	if (refcount == 1) {
-		WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
-		I915_WRITE(reg, new_val);
-		POSTING_READ(reg);
-		udelay(20);
-	} else {
-		WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
+		pll->enable(dev_priv, pll);
 	}
 }
 
@@ -1180,6 +1154,18 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
+			       struct intel_shared_dpll *pll)
+{
+	uint32_t cur_val;
+
+	cur_val = I915_READ(WRPLL_CTL(pll->id));
+	WARN(cur_val & WRPLL_PLL_ENABLE, "%s already enabled\n", pll->name);
+	I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
+	POSTING_READ(WRPLL_CTL(pll->id));
+	udelay(20);
+}
+
 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
@@ -1222,6 +1208,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
 		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
+		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
 		dev_priv->shared_dplls[i].get_hw_state =
 			hsw_ddi_pll_get_hw_state;
 	}
-- 
1.8.1.4

[PATCH 64/66] drm/i915: Switch to common shared dpll framework for WRPLLs

[Daniel Vetter]

Mostly this patch is one big excersize in deleting code and asserts
which are no longer needed. Note that we still abuse the shared dpll
framework a bit since we call the enable/disable functions from the
crtc mode_set and off hooks. But changing the actual hardware sequence
will be done in the next step.

Note that besides the massive amount of changes in this patch the
places and order in which the low-level WRPLL code is called is
absolutely unchanged.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_drv.h      |   6 --
 drivers/gpu/drm/i915/i915_reg.h      |   1 +
 drivers/gpu/drm/i915/intel_ddi.c     | 142 ++++-------------------------------
 drivers/gpu/drm/i915/intel_display.c |  14 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
 5 files changed, 27 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bebc507f776b..73371161777b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -225,11 +225,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n);
 
-struct intel_ddi_plls {
-	int wrpll1_refcount;
-	int wrpll2_refcount;
-};
-
 /* Interface history:
  *
  * 1.1: Original.
@@ -1399,7 +1394,6 @@ struct drm_i915_private {
 
 	int num_shared_dpll;
 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
-	struct intel_ddi_plls ddi_plls;
 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
 	/* Reclocking support */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99051e6348b8..fcb1ca6eadb5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5529,6 +5529,7 @@ enum punit_power_well {
 #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
 #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
 #define  PORT_CLK_SEL_SPLL		(3<<29)
+#define  PORT_CLK_SEL_WRPLL(pll)	(((pll)+4)<<29)
 #define  PORT_CLK_SEL_WRPLL1		(4<<29)
 #define  PORT_CLK_SEL_WRPLL2		(5<<29)
 #define  PORT_CLK_SEL_NONE		(7<<29)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 21e451ea0c69..7386a1212e71 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -257,31 +257,12 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 
 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
-	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(intel_crtc);
-
-	switch (intel_crtc->config.ddi_pll_sel) {
-	case PORT_CLK_SEL_WRPLL1:
-		plls->wrpll1_refcount--;
-		if (plls->wrpll1_refcount == 0) {
-			pll->disable(dev_priv, pll);
-		}
-		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
-		break;
-	case PORT_CLK_SEL_WRPLL2:
-		plls->wrpll2_refcount--;
-		if (plls->wrpll2_refcount == 0) {
-			pll->disable(dev_priv, pll);
-		}
-		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
-		break;
-	}
+	if (intel_crtc_to_shared_dpll(intel_crtc))
+		intel_disable_shared_dpll(intel_crtc);
 
-	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
-	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
+	intel_put_shared_dpll(intel_crtc);
 }
 
 #define LC_FREQ 2700
@@ -601,17 +582,14 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
-	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 	int type = intel_encoder->type;
-	enum pipe pipe = intel_crtc->pipe;
 	int clock = intel_crtc->config.port_clock;
 
 	intel_ddi_put_crtc_pll(crtc);
 
 	if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_shared_dpll *pll;
-		uint32_t reg, val;
+		uint32_t val;
 		unsigned p, n2, r2;
 
 		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
@@ -620,79 +598,21 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		      WRPLL_DIVIDER_POST(p);
 
-		if (val == I915_READ(WRPLL_CTL1)) {
-			DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
-				      pipe_name(pipe));
-			reg = WRPLL_CTL1;
-		} else if (val == I915_READ(WRPLL_CTL2)) {
-			DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
-				      pipe_name(pipe));
-			reg = WRPLL_CTL2;
-		} else if (plls->wrpll1_refcount == 0) {
-			DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
-				      pipe_name(pipe));
-			reg = WRPLL_CTL1;
-		} else if (plls->wrpll2_refcount == 0) {
-			DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
-				      pipe_name(pipe));
-			reg = WRPLL_CTL2;
-		} else {
-			DRM_ERROR("No WRPLLs available!\n");
-			return false;
-		}
+		intel_crtc->config.dpll_hw_state.wrpll = val;
 
-		DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
-			      clock, p, n2, r2);
-
-		if (reg == WRPLL_CTL1) {
-			plls->wrpll1_refcount++;
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
-			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
-		} else {
-			plls->wrpll2_refcount++;
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
-			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
+		pll = intel_get_shared_dpll(intel_crtc);
+		if (pll == NULL) {
+			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+					 pipe_name(intel_crtc->pipe));
+			return false;
 		}
 
-		intel_crtc->config.dpll_hw_state.wrpll = val;
-
-		pll = &dev_priv->shared_dplls[intel_crtc->config.shared_dpll];
-		pll->hw_state.wrpll = val;
+		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 	}
 
 	return true;
 }
 
-/*
- * To be called after intel_ddi_pll_select(). That one selects the PLL to be
- * used, this one actually enables the PLL.
- */
-void intel_ddi_pll_enable(struct intel_crtc *crtc)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
-	int refcount;
-	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-
-	switch (crtc->config.ddi_pll_sel) {
-	case PORT_CLK_SEL_WRPLL1:
-	case PORT_CLK_SEL_WRPLL2:
-		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
-			refcount = plls->wrpll1_refcount;
-		} else {
-			refcount = plls->wrpll2_refcount;
-		}
-		break;
-	default:
-		return;
-	}
-
-	if (refcount == 1) {
-		pll->enable(dev_priv, pll);
-	}
-}
-
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
@@ -929,35 +849,6 @@ static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	return intel_ddi_get_port_state(encoder, pipe, port);
 }
 
-void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	enum pipe pipe;
-	struct intel_crtc *intel_crtc;
-
-	dev_priv->ddi_plls.wrpll1_refcount = 0;
-	dev_priv->ddi_plls.wrpll2_refcount = 0;
-
-	for_each_pipe(pipe) {
-		intel_crtc =
-			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-
-		if (!intel_crtc->active) {
-			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
-			continue;
-		}
-
-		switch (intel_crtc->config.ddi_pll_sel) {
-		case PORT_CLK_SEL_WRPLL1:
-			dev_priv->ddi_plls.wrpll1_refcount++;
-			break;
-		case PORT_CLK_SEL_WRPLL2:
-			dev_priv->ddi_plls.wrpll2_refcount++;
-			break;
-		}
-	}
-}
-
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
@@ -1157,10 +1048,6 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
-	uint32_t cur_val;
-
-	cur_val = I915_READ(WRPLL_CTL(pll->id));
-	WARN(cur_val & WRPLL_PLL_ENABLE, "%s already enabled\n", pll->name);
 	I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
 	POSTING_READ(WRPLL_CTL(pll->id));
 	udelay(20);
@@ -1172,7 +1059,6 @@ static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	uint32_t val;
 
 	val = I915_READ(WRPLL_CTL(pll->id));
-	WARN_ON(!(val & WRPLL_PLL_ENABLE));
 	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
 	POSTING_READ(WRPLL_CTL(pll->id));
 }
@@ -1200,11 +1086,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
 	uint32_t val = I915_READ(LCPLL_CTL);
 	int i;
 
-	/* Dummy setup until everything is moved over to avoid upsetting the hw
-	 * state cross checker. */
-	dev_priv->num_shared_dpll = 0;
+	dev_priv->num_shared_dpll = 2;
 
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		dev_priv->shared_dplls[i].id = i;
 		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
 		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b890c97f1312..2fd77eba57f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1599,7 +1599,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
 	pll->on = true;
 }
 
-static void intel_disable_shared_dpll(struct intel_crtc *crtc)
+void intel_disable_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3232,7 +3232,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
-static void intel_put_shared_dpll(struct intel_crtc *crtc)
+void intel_put_shared_dpll(struct intel_crtc *crtc)
 {
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
 
@@ -3252,7 +3252,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
 	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
 }
 
-static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
@@ -7001,7 +7001,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (!intel_ddi_pll_select(intel_crtc))
 		return -EINVAL;
-	intel_ddi_pll_enable(intel_crtc);
+
+	if (intel_crtc_to_shared_dpll(intel_crtc))
+		intel_enable_shared_dpll(intel_crtc);
 
 	intel_crtc->lowfreq_avail = false;
 
@@ -11531,10 +11533,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			      crtc->active ? "enabled" : "disabled");
 	}
 
-	/* FIXME: Smash this into the new shared dpll infrastructure. */
-	if (HAS_DDI(dev))
-		intel_ddi_setup_hw_pll_state(dev);
-
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e1d079fe47ea..acd32e8e5e13 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -682,9 +682,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 				       enum transcoder cpu_transcoder);
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
-void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 bool intel_ddi_pll_select(struct intel_crtc *crtc);
-void intel_ddi_pll_enable(struct intel_crtc *crtc);
 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
@@ -740,12 +738,19 @@ __intel_framebuffer_create(struct drm_device *dev,
 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
+
+/* shared dpll functions */
 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			struct intel_shared_dpll *pll,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+void intel_disable_shared_dpll(struct intel_crtc *crtc);
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
+void intel_put_shared_dpll(struct intel_crtc *crtc);
+
+/* modesetting asserts */
 void assert_pll(struct drm_i915_private *dev_priv,
 		enum pipe pipe, bool state);
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
-- 
1.8.1.4

[PATCH 65/66] drm/i915: Only touch WRPLL hw state in enable/disable hooks

[Daniel Vetter]

To be able to do this we need to separately keep track of how many
crtcs need a given WRPLL and how many actually actively use it. The
common shared dpll framework already has all this, including massive
state readout and cross checking. Which allows us to do this switch in
a fairly small patch.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 12 +-----------
 drivers/gpu/drm/i915/intel_display.c | 16 +++++++---------
 drivers/gpu/drm/i915/intel_drv.h     |  2 --
 3 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7386a1212e71..97f9cd6dbee1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -255,16 +255,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 	return ret;
 }
 
-void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
-{
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-	if (intel_crtc_to_shared_dpll(intel_crtc))
-		intel_disable_shared_dpll(intel_crtc);
-
-	intel_put_shared_dpll(intel_crtc);
-}
-
 #define LC_FREQ 2700
 #define LC_FREQ_2K (LC_FREQ * 2000)
 
@@ -585,7 +575,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 	int type = intel_encoder->type;
 	int clock = intel_crtc->config.port_clock;
 
-	intel_ddi_put_crtc_pll(crtc);
+	intel_put_shared_dpll(intel_crtc);
 
 	if (type == INTEL_OUTPUT_HDMI) {
 		struct intel_shared_dpll *pll;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2fd77eba57f3..e0bd0f94e43e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3673,6 +3673,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->active)
 		return;
 
+	if (intel_crtc_to_shared_dpll(intel_crtc))
+		intel_enable_shared_dpll(intel_crtc);
+
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
@@ -3846,6 +3849,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	intel_update_fbc(dev);
 	intel_edp_psr_update(dev);
 	mutex_unlock(&dev->struct_mutex);
+
+	if (intel_crtc_to_shared_dpll(intel_crtc))
+		intel_disable_shared_dpll(intel_crtc);
 }
 
 static void ironlake_crtc_off(struct drm_crtc *crtc)
@@ -3854,11 +3860,6 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
 	intel_put_shared_dpll(intel_crtc);
 }
 
-static void haswell_crtc_off(struct drm_crtc *crtc)
-{
-	intel_ddi_put_crtc_pll(crtc);
-}
-
 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
 {
 	if (!enable && intel_crtc->overlay) {
@@ -7002,9 +7003,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	if (!intel_ddi_pll_select(intel_crtc))
 		return -EINVAL;
 
-	if (intel_crtc_to_shared_dpll(intel_crtc))
-		intel_enable_shared_dpll(intel_crtc);
-
 	intel_crtc->lowfreq_avail = false;
 
 	return 0;
@@ -10904,7 +10902,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
-		dev_priv->display.off = haswell_crtc_off;
+		dev_priv->display.off = ironlake_crtc_off;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index acd32e8e5e13..81a7813fc78b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -683,7 +683,6 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 bool intel_ddi_pll_select(struct intel_crtc *crtc);
-void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
@@ -746,7 +745,6 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-void intel_disable_shared_dpll(struct intel_crtc *crtc);
 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 void intel_put_shared_dpll(struct intel_crtc *crtc);
 
-- 
1.8.1.4

[PATCH 66/66] drm/i915: runtime PM support for DPMS

[Daniel Vetter]

Keeping track of the power domains is a bit messy since crtc->active
is currently updated by the platform hooks, but we need to be aware of
which state transition exactly is going on. Maybe we simply need to
shovel all the power domain handling down into platform code to
simplify this. But doing that requires some more auditing since
currently the ->mode_set callbacks still read some random registers
(to e.g. figure out the reference clocks).

Also note that intel_crtc_update_dpms is always call first/last even
for encoders which have their own dpms functions. Hence we really only
need to update this place here.

Being a quick "does it blow up?" run not really tested yet.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e0bd0f94e43e..1b5d6b099b37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4478,16 +4478,34 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *intel_encoder;
+	enum intel_display_power_domain domain;
+	unsigned long domains;
 	bool enable = false;
 
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
 		enable |= intel_encoder->connectors_active;
 
-	if (enable)
-		dev_priv->display.crtc_enable(crtc);
-	else
-		dev_priv->display.crtc_disable(crtc);
+	if (enable) {
+		if (!intel_crtc->active) {
+			domains = get_crtc_power_domains(crtc);
+			for_each_power_domain(domain, domains)
+				intel_display_power_get(dev_priv, domain);
+			intel_crtc->enabled_power_domains = domains;
+
+			dev_priv->display.crtc_enable(crtc);
+		}
+	} else {
+		if (intel_crtc->active) {
+			dev_priv->display.crtc_disable(crtc);
+
+			domains = intel_crtc->enabled_power_domains;
+			for_each_power_domain(domain, domains)
+				intel_display_power_put(dev_priv, domain);
+			intel_crtc->enabled_power_domains = 0;
+		}
+	}
 
 	intel_crtc_update_sarea(crtc, enable);
 }
-- 
1.8.1.4

Re: [PATCH 00/66] runtime pm for DPMS

[Daniel Vetter]

Ok, review assignements. Please complain if you don't have the
bandwidth so that I can find someone else.

On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>
> Daniel Vetter (66):
>   drm/i915: Make encoder->mode_set callbacks optional
>   drm/i915/dvo: Remove ->mode_set callback
>   drm/i915/tv: extract set_tv_mode_timings
>   drm/i915/tv: extract set_color_conversion
>   drm/i915/tv: De-magic device check
>   drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
>   drm/i915/tv: Remove ->mode_set callback
>   drm/i915/crt: Remove ->mode_set callback
>   drm/i915/sdvo: Remove ->mode_set callback
>
> Removal of encoder->mode_set callbacks, part 1

Reviewer: Imre

>   drm/i915/hdmi: Enable hdmi mode on g4x, too
>   drm/i915: Track hdmi mode in the pipe config
>   drm/i915/sdvo: Use pipe_config->limited_color_range consistently
>   drm/i915: state readout and cross checking for limited_color_range
>   drm/i915/sdvo: use config->has_hdmi_sink
>   drm/i915: Simplify audio handling on DDI ports
>   drm/i915: Track has_audio in the pipe config
>   drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
>   drm/i915/dp: Remove ->mode_set callback
>   drm/i915/hdmi: Remove redundant IS_VLV checks
>   drm/i915/hdmi: Remove ->mode_set callback
>
> Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
> interludes to move a bit of the hdmi/audio state into the pipe config.

Reviewer: Naresh Kumar


>   drm/i915/lvds: Remove ->mode_set callback
>   drm/i915/ddi: Remove ->mode_set callback
>   drm/i915/dsi: Remove ->mode_set callback
>   drm/i915: Stop calling encoder->mode_set
>
> Final removals of encoder->mode_set callbacks

Reviewer: Imre

>   drm/i915: Make ->update_primary_plane infallible
>   drm/i915: More cargo-culted locking for intel_update_fbc
>   drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
>   drm/i915: Inline set_base into crtc_mode_set
>   drm/i915: Move fb pinning into __intel_set_mode
>
> Some shuffling to get the primary->fb handling out of crtc mode_set callbacks

Reviewer: Akash Goel

>   drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
>   drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
>   drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
>   drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
>   drm/i915: Extract i9xx_set_pll_dividers
>   drm/i915: Extract vlv_prepare_pll
>
> gmch pll moved out of crtc mode_set callbacks into ->enable hooks

Reviewer: Shobhit Kumar

>   drm/i915: Only update shared dpll state when needed
>   drm/i915: Extract intel_prepare_shared_dpll
>   drm/i915: s/ironlake_/intel_ for the enable_share_dpll function
>
> Prep polish on the existing shared_dpll code

Reviewer: Damien (same comment as below)

>   drm/i915: Check hw state in assert_can_disable_lcpll
>   drm/i915: Remove spll_refcount for hsw
>   drm/i915: Clean up WRPLL/SPLL #defines
>   drm/i915: Make intel_wait_for_pipe_off static
>   drm/i915: Disable pipe before ports on ilk
>   drm/i915: Pass port explicitly to intel_ddi_get_hw_state
>   drm/i915: Unexport intel_ddi_connector_get_hw_state
>   drm/i915: Move hsw_fdi_link_train into intel_crt.c
>   drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
>   drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
>   drm/i915: Move lpt_pch_enable int hsw_crt_enable
>   drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
>   drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
>   drm/i915: Move pch fifo underrun report re-enabling into
>     hsw_crt_post_disable
>   drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
>   drm/i915: Move SPLL disabling into hsw_crt_post_disable
>
> Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
> on haswell. This has the nice upshot to make SPLL logically a port-private clock
> and so removes it from further considerations.

Reviewer: Paulo

>   drm/i915: Add a debugfs file for the shared dpll state
>   drm/i915: Move ddi_pll_sel into the pipe config
>   drm/i915: State readout and cross-checking for ddi_pll_sel
>   drm/i915: Precompute static ddi_pll_sel values in encoders
>   drm/i915: Basic shared dpll support for WRPLLs
>   drm/i915: Document that the pll->mode_set hook is optional
>   drm/i915: State readout support for WRPLLs
>   drm/i915: ->disable hook for WRPLLs
>   drm/i915: ->enable hook for WRPLLs
>   drm/i915: Switch to common shared dpll framework for WRPLLs
>   drm/i915: Only touch WRPLL hw state in enable/disable hooks
>
> Convert wrpll handling to the common shared_dpll framework. We need this since
> runtime pm for dpms requires us to separately track pll refernces from crtcs and
> active usage by crtcs

Reviewer: Damien (maybe find someone from the vpg guys who do the pll
stuff for your project instead)

>   drm/i915: runtime PM support for DPMS

Reviewer: Paulo/Imre
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 00/66] runtime pm for DPMS

[Shobhit Kumar]

>>    drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
>>    drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
>>    drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
>>    drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
>>    drm/i915: Extract i9xx_set_pll_dividers
>>    drm/i915: Extract vlv_prepare_pll
>>
>> gmch pll moved out of crtc mode_set callbacks into ->enable hooks
>
> Reviewer: Shobhit Kumar

I will be on vacation till next weekend, so will get to these after 
that. Keep on my name if that is okay.

Regards
Shobhit

Re: [PATCH 00/66] runtime pm for DPMS

[Imre Deak]

On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote:
> Ok, review assignements. Please complain if you don't have the
> bandwidth so that I can find someone else.
> 
> On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> >
> > Daniel Vetter (66):
> >   drm/i915: Make encoder->mode_set callbacks optional
> >   drm/i915/dvo: Remove ->mode_set callback
> >   drm/i915/tv: extract set_tv_mode_timings
> >   drm/i915/tv: extract set_color_conversion
> >   drm/i915/tv: De-magic device check
> >   drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
> >   drm/i915/tv: Remove ->mode_set callback
> >   drm/i915/crt: Remove ->mode_set callback
> >   drm/i915/sdvo: Remove ->mode_set callback
> >
> > Removal of encoder->mode_set callbacks, part 1
> 
> Reviewer: Imre

1-9 look good to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>


> >   drm/i915/hdmi: Enable hdmi mode on g4x, too
> >   drm/i915: Track hdmi mode in the pipe config
> >   drm/i915/sdvo: Use pipe_config->limited_color_range consistently
> >   drm/i915: state readout and cross checking for limited_color_range
> >   drm/i915/sdvo: use config->has_hdmi_sink
> >   drm/i915: Simplify audio handling on DDI ports
> >   drm/i915: Track has_audio in the pipe config
> >   drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
> >   drm/i915/dp: Remove ->mode_set callback
> >   drm/i915/hdmi: Remove redundant IS_VLV checks
> >   drm/i915/hdmi: Remove ->mode_set callback
> >
> > Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
> > interludes to move a bit of the hdmi/audio state into the pipe config.
> 
> Reviewer: Naresh Kumar
> 
> 
> >   drm/i915/lvds: Remove ->mode_set callback
> >   drm/i915/ddi: Remove ->mode_set callback
> >   drm/i915/dsi: Remove ->mode_set callback
> >   drm/i915: Stop calling encoder->mode_set
> >
> > Final removals of encoder->mode_set callbacks
> 
> Reviewer: Imre
> 
> >   drm/i915: Make ->update_primary_plane infallible
> >   drm/i915: More cargo-culted locking for intel_update_fbc
> >   drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
> >   drm/i915: Inline set_base into crtc_mode_set
> >   drm/i915: Move fb pinning into __intel_set_mode
> >
> > Some shuffling to get the primary->fb handling out of crtc mode_set callbacks
> 
> Reviewer: Akash Goel
> 
> >   drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
> >   drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
> >   drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
> >   drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
> >   drm/i915: Extract i9xx_set_pll_dividers
> >   drm/i915: Extract vlv_prepare_pll
> >
> > gmch pll moved out of crtc mode_set callbacks into ->enable hooks
> 
> Reviewer: Shobhit Kumar
> 
> >   drm/i915: Only update shared dpll state when needed
> >   drm/i915: Extract intel_prepare_shared_dpll
> >   drm/i915: s/ironlake_/intel_ for the enable_share_dpll function
> >
> > Prep polish on the existing shared_dpll code
> 
> Reviewer: Damien (same comment as below)
> 
> >   drm/i915: Check hw state in assert_can_disable_lcpll
> >   drm/i915: Remove spll_refcount for hsw
> >   drm/i915: Clean up WRPLL/SPLL #defines
> >   drm/i915: Make intel_wait_for_pipe_off static
> >   drm/i915: Disable pipe before ports on ilk
> >   drm/i915: Pass port explicitly to intel_ddi_get_hw_state
> >   drm/i915: Unexport intel_ddi_connector_get_hw_state
> >   drm/i915: Move hsw_fdi_link_train into intel_crt.c
> >   drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
> >   drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
> >   drm/i915: Move lpt_pch_enable int hsw_crt_enable
> >   drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
> >   drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
> >   drm/i915: Move pch fifo underrun report re-enabling into
> >     hsw_crt_post_disable
> >   drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
> >   drm/i915: Move SPLL disabling into hsw_crt_post_disable
> >
> > Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
> > on haswell. This has the nice upshot to make SPLL logically a port-private clock
> > and so removes it from further considerations.
> 
> Reviewer: Paulo
> 
> >   drm/i915: Add a debugfs file for the shared dpll state
> >   drm/i915: Move ddi_pll_sel into the pipe config
> >   drm/i915: State readout and cross-checking for ddi_pll_sel
> >   drm/i915: Precompute static ddi_pll_sel values in encoders
> >   drm/i915: Basic shared dpll support for WRPLLs
> >   drm/i915: Document that the pll->mode_set hook is optional
> >   drm/i915: State readout support for WRPLLs
> >   drm/i915: ->disable hook for WRPLLs
> >   drm/i915: ->enable hook for WRPLLs
> >   drm/i915: Switch to common shared dpll framework for WRPLLs
> >   drm/i915: Only touch WRPLL hw state in enable/disable hooks
> >
> > Convert wrpll handling to the common shared_dpll framework. We need this since
> > runtime pm for dpms requires us to separately track pll refernces from crtcs and
> > active usage by crtcs
> 
> Reviewer: Damien (maybe find someone from the vpg guys who do the pll
> stuff for your project instead)
> 
> >   drm/i915: runtime PM support for DPMS
> 
> Reviewer: Paulo/Imre

Re: [PATCH 00/66] runtime pm for DPMS

[Daniel Vetter]

On Wed, Apr 30, 2014 at 5:36 PM, Shobhit Kumar <shobhit.kumar@intel.com> wrote:
>>>    drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
>>>    drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
>>>    drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
>>>    drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
>>>    drm/i915: Extract i9xx_set_pll_dividers
>>>    drm/i915: Extract vlv_prepare_pll
>>>
>>> gmch pll moved out of crtc mode_set callbacks into ->enable hooks
>>
>>
>> Reviewer: Shobhit Kumar
>
>
> I will be on vacation till next weekend, so will get to these after that.
> Keep on my name if that is okay.

That's ok imo, but thanks a lot for the heads-up.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 00/66] runtime pm for DPMS

[Daniel Vetter]

On Wed, Apr 30, 2014 at 6:38 PM, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote:
>> Ok, review assignements. Please complain if you don't have the
>> bandwidth so that I can find someone else.
>>
>> On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>> >
>> > Daniel Vetter (66):
>> >   drm/i915: Make encoder->mode_set callbacks optional
>> >   drm/i915/dvo: Remove ->mode_set callback
>> >   drm/i915/tv: extract set_tv_mode_timings
>> >   drm/i915/tv: extract set_color_conversion
>> >   drm/i915/tv: De-magic device check
>> >   drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
>> >   drm/i915/tv: Remove ->mode_set callback
>> >   drm/i915/crt: Remove ->mode_set callback
>> >   drm/i915/sdvo: Remove ->mode_set callback
>> >
>> > Removal of encoder->mode_set callbacks, part 1
>>
>> Reviewer: Imre
>
> 1-9 look good to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks for the review, merged the first 9 patches.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 00/66] runtime pm for DPMS

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 5447 bytes --]

On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote:
> Ok, review assignements. Please complain if you don't have the
> bandwidth so that I can find someone else.
> 
> On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> >
> > Daniel Vetter (66):
> >   drm/i915: Make encoder->mode_set callbacks optional
> >   drm/i915/dvo: Remove ->mode_set callback
> >   drm/i915/tv: extract set_tv_mode_timings
> >   drm/i915/tv: extract set_color_conversion
> >   drm/i915/tv: De-magic device check
> >   drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
> >   drm/i915/tv: Remove ->mode_set callback
> >   drm/i915/crt: Remove ->mode_set callback
> >   drm/i915/sdvo: Remove ->mode_set callback
> >
> > Removal of encoder->mode_set callbacks, part 1
> 
> Reviewer: Imre
> 
> >   drm/i915/hdmi: Enable hdmi mode on g4x, too
> >   drm/i915: Track hdmi mode in the pipe config
> >   drm/i915/sdvo: Use pipe_config->limited_color_range consistently
> >   drm/i915: state readout and cross checking for limited_color_range
> >   drm/i915/sdvo: use config->has_hdmi_sink
> >   drm/i915: Simplify audio handling on DDI ports
> >   drm/i915: Track has_audio in the pipe config
> >   drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
> >   drm/i915/dp: Remove ->mode_set callback
> >   drm/i915/hdmi: Remove redundant IS_VLV checks
> >   drm/i915/hdmi: Remove ->mode_set callback
> >
> > Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
> > interludes to move a bit of the hdmi/audio state into the pipe config.
> 
> Reviewer: Naresh Kumar
> 
> 
> >   drm/i915/lvds: Remove ->mode_set callback
> >   drm/i915/ddi: Remove ->mode_set callback
> >   drm/i915/dsi: Remove ->mode_set callback
> >   drm/i915: Stop calling encoder->mode_set
> >
> > Final removals of encoder->mode_set callbacks
> 
> Reviewer: Imre

On patches 21-24:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> 
> >   drm/i915: Make ->update_primary_plane infallible
> >   drm/i915: More cargo-culted locking for intel_update_fbc
> >   drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
> >   drm/i915: Inline set_base into crtc_mode_set
> >   drm/i915: Move fb pinning into __intel_set_mode
> >
> > Some shuffling to get the primary->fb handling out of crtc mode_set callbacks
> 
> Reviewer: Akash Goel
> 
> >   drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
> >   drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
> >   drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
> >   drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
> >   drm/i915: Extract i9xx_set_pll_dividers
> >   drm/i915: Extract vlv_prepare_pll
> >
> > gmch pll moved out of crtc mode_set callbacks into ->enable hooks
> 
> Reviewer: Shobhit Kumar
> 
> >   drm/i915: Only update shared dpll state when needed
> >   drm/i915: Extract intel_prepare_shared_dpll
> >   drm/i915: s/ironlake_/intel_ for the enable_share_dpll function
> >
> > Prep polish on the existing shared_dpll code
> 
> Reviewer: Damien (same comment as below)
> 
> >   drm/i915: Check hw state in assert_can_disable_lcpll
> >   drm/i915: Remove spll_refcount for hsw
> >   drm/i915: Clean up WRPLL/SPLL #defines
> >   drm/i915: Make intel_wait_for_pipe_off static
> >   drm/i915: Disable pipe before ports on ilk
> >   drm/i915: Pass port explicitly to intel_ddi_get_hw_state
> >   drm/i915: Unexport intel_ddi_connector_get_hw_state
> >   drm/i915: Move hsw_fdi_link_train into intel_crt.c
> >   drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
> >   drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
> >   drm/i915: Move lpt_pch_enable int hsw_crt_enable
> >   drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
> >   drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
> >   drm/i915: Move pch fifo underrun report re-enabling into
> >     hsw_crt_post_disable
> >   drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
> >   drm/i915: Move SPLL disabling into hsw_crt_post_disable
> >
> > Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
> > on haswell. This has the nice upshot to make SPLL logically a port-private clock
> > and so removes it from further considerations.
> 
> Reviewer: Paulo
> 
> >   drm/i915: Add a debugfs file for the shared dpll state
> >   drm/i915: Move ddi_pll_sel into the pipe config
> >   drm/i915: State readout and cross-checking for ddi_pll_sel
> >   drm/i915: Precompute static ddi_pll_sel values in encoders
> >   drm/i915: Basic shared dpll support for WRPLLs
> >   drm/i915: Document that the pll->mode_set hook is optional
> >   drm/i915: State readout support for WRPLLs
> >   drm/i915: ->disable hook for WRPLLs
> >   drm/i915: ->enable hook for WRPLLs
> >   drm/i915: Switch to common shared dpll framework for WRPLLs
> >   drm/i915: Only touch WRPLL hw state in enable/disable hooks
> >
> > Convert wrpll handling to the common shared_dpll framework. We need this since
> > runtime pm for dpms requires us to separately track pll refernces from crtcs and
> > active usage by crtcs
> 
> Reviewer: Damien (maybe find someone from the vpg guys who do the pll
> stuff for your project instead)
> 
> >   drm/i915: runtime PM support for DPMS
> 
> Reviewer: Paulo/Imre


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Re: [PATCH 00/66] runtime pm for DPMS

[Naresh Kumar Kachhi]

On 04/30/2014 10:08 PM, Imre Deak wrote:
> On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote:
>> Ok, review assignements. Please complain if you don't have the
>> bandwidth so that I can find someone else.
>>
>> On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>>> Daniel Vetter (66):
>>>    drm/i915: Make encoder->mode_set callbacks optional
>>>    drm/i915/dvo: Remove ->mode_set callback
>>>    drm/i915/tv: extract set_tv_mode_timings
>>>    drm/i915/tv: extract set_color_conversion
>>>    drm/i915/tv: De-magic device check
>>>    drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
>>>    drm/i915/tv: Remove ->mode_set callback
>>>    drm/i915/crt: Remove ->mode_set callback
>>>    drm/i915/sdvo: Remove ->mode_set callback
>>>
>>> Removal of encoder->mode_set callbacks, part 1
>> Reviewer: Imre
> 1-9 look good to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
>
>>>    drm/i915/hdmi: Enable hdmi mode on g4x, too
>>>    drm/i915: Track hdmi mode in the pipe config
>>>    drm/i915/sdvo: Use pipe_config->limited_color_range consistently
>>>    drm/i915: state readout and cross checking for limited_color_range
>>>    drm/i915/sdvo: use config->has_hdmi_sink
>>>    drm/i915: Simplify audio handling on DDI ports
>>>    drm/i915: Track has_audio in the pipe config
>>>    drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
>>>    drm/i915/dp: Remove ->mode_set callback
>>>    drm/i915/hdmi: Remove redundant IS_VLV checks
>>>    drm/i915/hdmi: Remove ->mode_set callback
>>>
>>> Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
>>> interludes to move a bit of the hdmi/audio state into the pipe config.
>> Reviewer: Naresh Kumar
>>
reviewed 10-20, looks good.
Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>

>>>    drm/i915/lvds: Remove ->mode_set callback
>>>    drm/i915/ddi: Remove ->mode_set callback
>>>    drm/i915/dsi: Remove ->mode_set callback
>>>    drm/i915: Stop calling encoder->mode_set
>>>
>>> Final removals of encoder->mode_set callbacks
>> Reviewer: Imre
>>
>>>    drm/i915: Make ->update_primary_plane infallible
>>>    drm/i915: More cargo-culted locking for intel_update_fbc
>>>    drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
>>>    drm/i915: Inline set_base into crtc_mode_set
>>>    drm/i915: Move fb pinning into __intel_set_mode
>>>
>>> Some shuffling to get the primary->fb handling out of crtc mode_set callbacks
>> Reviewer: Akash Goel
>>
>>>    drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
>>>    drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
>>>    drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
>>>    drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
>>>    drm/i915: Extract i9xx_set_pll_dividers
>>>    drm/i915: Extract vlv_prepare_pll
>>>
>>> gmch pll moved out of crtc mode_set callbacks into ->enable hooks
>> Reviewer: Shobhit Kumar
>>
>>>    drm/i915: Only update shared dpll state when needed
>>>    drm/i915: Extract intel_prepare_shared_dpll
>>>    drm/i915: s/ironlake_/intel_ for the enable_share_dpll function
>>>
>>> Prep polish on the existing shared_dpll code
>> Reviewer: Damien (same comment as below)
>>
>>>    drm/i915: Check hw state in assert_can_disable_lcpll
>>>    drm/i915: Remove spll_refcount for hsw
>>>    drm/i915: Clean up WRPLL/SPLL #defines
>>>    drm/i915: Make intel_wait_for_pipe_off static
>>>    drm/i915: Disable pipe before ports on ilk
>>>    drm/i915: Pass port explicitly to intel_ddi_get_hw_state
>>>    drm/i915: Unexport intel_ddi_connector_get_hw_state
>>>    drm/i915: Move hsw_fdi_link_train into intel_crt.c
>>>    drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
>>>    drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
>>>    drm/i915: Move lpt_pch_enable int hsw_crt_enable
>>>    drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
>>>    drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
>>>    drm/i915: Move pch fifo underrun report re-enabling into
>>>      hsw_crt_post_disable
>>>    drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
>>>    drm/i915: Move SPLL disabling into hsw_crt_post_disable
>>>
>>> Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
>>> on haswell. This has the nice upshot to make SPLL logically a port-private clock
>>> and so removes it from further considerations.
>> Reviewer: Paulo
>>
>>>    drm/i915: Add a debugfs file for the shared dpll state
>>>    drm/i915: Move ddi_pll_sel into the pipe config
>>>    drm/i915: State readout and cross-checking for ddi_pll_sel
>>>    drm/i915: Precompute static ddi_pll_sel values in encoders
>>>    drm/i915: Basic shared dpll support for WRPLLs
>>>    drm/i915: Document that the pll->mode_set hook is optional
>>>    drm/i915: State readout support for WRPLLs
>>>    drm/i915: ->disable hook for WRPLLs
>>>    drm/i915: ->enable hook for WRPLLs
>>>    drm/i915: Switch to common shared dpll framework for WRPLLs
>>>    drm/i915: Only touch WRPLL hw state in enable/disable hooks
>>>
>>> Convert wrpll handling to the common shared_dpll framework. We need this since
>>> runtime pm for dpms requires us to separately track pll refernces from crtcs and
>>> active usage by crtcs
>> Reviewer: Damien (maybe find someone from the vpg guys who do the pll
>> stuff for your project instead)
>>
>>>    drm/i915: runtime PM support for DPMS
>> Reviewer: Paulo/Imre
>

Re: [PATCH 24/66] drm/i915: Stop calling encoder->mode_set

[Daniel Vetter]

On Thu, Apr 24, 2014 at 11:55:00PM +0200, Daniel Vetter wrote:
> All the callbacks are gone now.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Merged up to this patch here, thanks everyone for the reviews.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 33 ++-------------------------------
>  1 file changed, 2 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f8ebe9b59746..dec4127a4738 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7202,35 +7202,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	return true;
>  }
>  
> -static int intel_crtc_mode_set(struct drm_crtc *crtc,
> -			       int x, int y,
> -			       struct drm_framebuffer *fb)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_encoder *encoder;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
> -	int ret;
> -
> -	ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
> -
> -	if (ret != 0)
> -		return ret;
> -
> -	for_each_encoder_on_crtc(dev, crtc, encoder) {
> -		DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
> -			encoder->base.base.id,
> -			drm_get_encoder_name(&encoder->base),
> -			mode->base.id, mode->name);
> -
> -		if (encoder->mode_set)
> -			encoder->mode_set(encoder);
> -	}
> -
> -	return 0;
> -}
> -
>  static struct {
>  	int clock;
>  	u32 config;
> @@ -9994,8 +9965,8 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  	 * on the DPLL.
>  	 */
>  	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
> -		ret = intel_crtc_mode_set(&intel_crtc->base,
> -					  x, y, fb);
> +		ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
> +						      x, y, fb);
>  		if (ret)
>  			goto done;
>  	}
> -- 
> 1.8.1.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS

[Jesse Barnes]

On Thu, 24 Apr 2014 23:55:42 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> +	if (enable) {
> +		if (!intel_crtc->active) {
> +			domains = get_crtc_power_domains(crtc);
> +			for_each_power_domain(domain, domains)
> +				intel_display_power_get(dev_priv, domain);
> +			intel_crtc->enabled_power_domains = domains;
> +
> +			dev_priv->display.crtc_enable(crtc);
> +		}
> +	} else {
> +		if (intel_crtc->active) {
> +			dev_priv->display.crtc_disable(crtc);
> +
> +			domains = intel_crtc->enabled_power_domains;
> +			for_each_power_domain(domain, domains)
> +				intel_display_power_put(dev_priv, domain);
> +			intel_crtc->enabled_power_domains = 0;
> +		}
> +	}

These branches could probably be cleaned up a bit.

But the power domain bits here got me thinking that maybe we can push
them down into the crtc_enable/disable functions instead.  That would
let us do the right thing per-platform and save us the
"get_crtc_power_domains" call which may not make sense on all platforms.

I haven't thought it through for the other power wells, but that type
of approach may make more sense than trying to abstract the wells at
the high level we're doing today, especially since things are likely to
get finer grained over time rather than coarser.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS

[Daniel Vetter]

On Fri, May 16, 2014 at 02:48:27PM -0700, Jesse Barnes wrote:
> On Thu, 24 Apr 2014 23:55:42 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > +	if (enable) {
> > +		if (!intel_crtc->active) {
> > +			domains = get_crtc_power_domains(crtc);
> > +			for_each_power_domain(domain, domains)
> > +				intel_display_power_get(dev_priv, domain);
> > +			intel_crtc->enabled_power_domains = domains;
> > +
> > +			dev_priv->display.crtc_enable(crtc);
> > +		}
> > +	} else {
> > +		if (intel_crtc->active) {
> > +			dev_priv->display.crtc_disable(crtc);
> > +
> > +			domains = intel_crtc->enabled_power_domains;
> > +			for_each_power_domain(domain, domains)
> > +				intel_display_power_put(dev_priv, domain);
> > +			intel_crtc->enabled_power_domains = 0;
> > +		}
> > +	}
> 
> These branches could probably be cleaned up a bit.
> 
> But the power domain bits here got me thinking that maybe we can push
> them down into the crtc_enable/disable functions instead.  That would
> let us do the right thing per-platform and save us the
> "get_crtc_power_domains" call which may not make sense on all platforms.
> 
> I haven't thought it through for the other power wells, but that type
> of approach may make more sense than trying to abstract the wells at
> the high level we're doing today, especially since things are likely to
> get finer grained over time rather than coarser.

Had the same idea but then things get ugly since since the power domain
grabbing in the modeset sequence is a bit convoluted (for historical
reasons). So would require a bit of unwinding.

Also this gives us a much clearer bisect point imo.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS

[Jesse Barnes]

On Sat, 17 May 2014 00:19:09 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Fri, May 16, 2014 at 02:48:27PM -0700, Jesse Barnes wrote:
> > On Thu, 24 Apr 2014 23:55:42 +0200
> > Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > 
> > > +	if (enable) {
> > > +		if (!intel_crtc->active) {
> > > +			domains = get_crtc_power_domains(crtc);
> > > +			for_each_power_domain(domain, domains)
> > > +				intel_display_power_get(dev_priv, domain);
> > > +			intel_crtc->enabled_power_domains = domains;
> > > +
> > > +			dev_priv->display.crtc_enable(crtc);
> > > +		}
> > > +	} else {
> > > +		if (intel_crtc->active) {
> > > +			dev_priv->display.crtc_disable(crtc);
> > > +
> > > +			domains = intel_crtc->enabled_power_domains;
> > > +			for_each_power_domain(domain, domains)
> > > +				intel_display_power_put(dev_priv, domain);
> > > +			intel_crtc->enabled_power_domains = 0;
> > > +		}
> > > +	}
> > 
> > These branches could probably be cleaned up a bit.
> > 
> > But the power domain bits here got me thinking that maybe we can push
> > them down into the crtc_enable/disable functions instead.  That would
> > let us do the right thing per-platform and save us the
> > "get_crtc_power_domains" call which may not make sense on all platforms.
> > 
> > I haven't thought it through for the other power wells, but that type
> > of approach may make more sense than trying to abstract the wells at
> > the high level we're doing today, especially since things are likely to
> > get finer grained over time rather than coarser.
> 
> Had the same idea but then things get ugly since since the power domain
> grabbing in the modeset sequence is a bit convoluted (for historical
> reasons). So would require a bit of unwinding.
> 
> Also this gives us a much clearer bisect point imo.

Yeah no doubt, not suggesting you change it as part of this series...
but overall it's something to consider for a future rewrite of our
power well code. :)

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 00/66] runtime pm for DPMS

[Akash Goel]

On Fri, 2014-05-16 at 14:09 +0530, Naresh Kumar Kachhi wrote:
> On 04/30/2014 10:08 PM, Imre Deak wrote:
> > On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote:
> >> Ok, review assignements. Please complain if you don't have the
> >> bandwidth so that I can find someone else.
> >>
> >> On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> >>> Daniel Vetter (66):
> >>>    drm/i915: Make encoder->mode_set callbacks optional
> >>>    drm/i915/dvo: Remove ->mode_set callback
> >>>    drm/i915/tv: extract set_tv_mode_timings
> >>>    drm/i915/tv: extract set_color_conversion
> >>>    drm/i915/tv: De-magic device check
> >>>    drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
> >>>    drm/i915/tv: Remove ->mode_set callback
> >>>    drm/i915/crt: Remove ->mode_set callback
> >>>    drm/i915/sdvo: Remove ->mode_set callback
> >>>
> >>> Removal of encoder->mode_set callbacks, part 1
> >> Reviewer: Imre
> > 1-9 look good to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> >
> >>>    drm/i915/hdmi: Enable hdmi mode on g4x, too
> >>>    drm/i915: Track hdmi mode in the pipe config
> >>>    drm/i915/sdvo: Use pipe_config->limited_color_range consistently
> >>>    drm/i915: state readout and cross checking for limited_color_range
> >>>    drm/i915/sdvo: use config->has_hdmi_sink
> >>>    drm/i915: Simplify audio handling on DDI ports
> >>>    drm/i915: Track has_audio in the pipe config
> >>>    drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
> >>>    drm/i915/dp: Remove ->mode_set callback
> >>>    drm/i915/hdmi: Remove redundant IS_VLV checks
> >>>    drm/i915/hdmi: Remove ->mode_set callback
> >>>
> >>> Removal of the encoder->mode_set callbacks for hdmi/sdvo/dp with small
> >>> interludes to move a bit of the hdmi/audio state into the pipe config.
> >> Reviewer: Naresh Kumar
> >>
> reviewed 10-20, looks good.
> Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
> 
> >>>    drm/i915/lvds: Remove ->mode_set callback
> >>>    drm/i915/ddi: Remove ->mode_set callback
> >>>    drm/i915/dsi: Remove ->mode_set callback
> >>>    drm/i915: Stop calling encoder->mode_set
> >>>
> >>> Final removals of encoder->mode_set callbacks
> >> Reviewer: Imre
> >>
> >>>    drm/i915: Make ->update_primary_plane infallible
> >>>    drm/i915: More cargo-culted locking for intel_update_fbc
> >>>    drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
> >>>    drm/i915: Inline set_base into crtc_mode_set
> >>>    drm/i915: Move fb pinning into __intel_set_mode
> >>>
> >>> Some shuffling to get the primary->fb handling out of crtc mode_set callbacks
> >> Reviewer: Akash Goel

Reviewed 25-29, looks fine.
Reviewed-by: Akash Goel <akash.goel@intel.com>

> >>
> >>>    drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
> >>>    drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
> >>>    drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
> >>>    drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
> >>>    drm/i915: Extract i9xx_set_pll_dividers
> >>>    drm/i915: Extract vlv_prepare_pll
> >>>
> >>> gmch pll moved out of crtc mode_set callbacks into ->enable hooks
> >> Reviewer: Shobhit Kumar
> >>
> >>>    drm/i915: Only update shared dpll state when needed
> >>>    drm/i915: Extract intel_prepare_shared_dpll
> >>>    drm/i915: s/ironlake_/intel_ for the enable_share_dpll function
> >>>
> >>> Prep polish on the existing shared_dpll code
> >> Reviewer: Damien (same comment as below)
> >>
> >>>    drm/i915: Check hw state in assert_can_disable_lcpll
> >>>    drm/i915: Remove spll_refcount for hsw
> >>>    drm/i915: Clean up WRPLL/SPLL #defines
> >>>    drm/i915: Make intel_wait_for_pipe_off static
> >>>    drm/i915: Disable pipe before ports on ilk
> >>>    drm/i915: Pass port explicitly to intel_ddi_get_hw_state
> >>>    drm/i915: Unexport intel_ddi_connector_get_hw_state
> >>>    drm/i915: Move hsw_fdi_link_train into intel_crt.c
> >>>    drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable
> >>>    drm/i915: Move the SPLL enabling into hsw_crt_pre_enable
> >>>    drm/i915: Move lpt_pch_enable int hsw_crt_enable
> >>>    drm/i915: Move the pch fifo underrun handling into hsw_crt_disable
> >>>    drm/i915: Move lpt_disable_pch_transcoder into the hsw crt encoder
> >>>    drm/i915: Move pch fifo underrun report re-enabling into
> >>>      hsw_crt_post_disable
> >>>    drm/i915: Move the hsw fdi disabling into hsw_crt_post_disable
> >>>    drm/i915: Move SPLL disabling into hsw_crt_post_disable
> >>>
> >>> Create a new hsw-specific crt encoder which subsumes the entire fdi/pch handling
> >>> on haswell. This has the nice upshot to make SPLL logically a port-private clock
> >>> and so removes it from further considerations.
> >> Reviewer: Paulo
> >>
> >>>    drm/i915: Add a debugfs file for the shared dpll state
> >>>    drm/i915: Move ddi_pll_sel into the pipe config
> >>>    drm/i915: State readout and cross-checking for ddi_pll_sel
> >>>    drm/i915: Precompute static ddi_pll_sel values in encoders
> >>>    drm/i915: Basic shared dpll support for WRPLLs
> >>>    drm/i915: Document that the pll->mode_set hook is optional
> >>>    drm/i915: State readout support for WRPLLs
> >>>    drm/i915: ->disable hook for WRPLLs
> >>>    drm/i915: ->enable hook for WRPLLs
> >>>    drm/i915: Switch to common shared dpll framework for WRPLLs
> >>>    drm/i915: Only touch WRPLL hw state in enable/disable hooks
> >>>
> >>> Convert wrpll handling to the common shared_dpll framework. We need this since
> >>> runtime pm for dpms requires us to separately track pll refernces from crtcs and
> >>> active usage by crtcs
> >> Reviewer: Damien (maybe find someone from the vpg guys who do the pll
> >> stuff for your project instead)
> >>
> >>>    drm/i915: runtime PM support for DPMS
> >> Reviewer: Paulo/Imre
> >
> 

Re: [PATCH 36/66] drm/i915: Only update shared dpll state when needed

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:12PM +0200, Daniel Vetter wrote:
> Instead of every time it isn't active: We only need to do that when
> the pll is currently unused, i.e. when pll->refcount == 0. For
> paranoia add a warning for the ibx case where plls have a fixed
> mapping and hence should always be unused after the call to
> intel_put_shared_dpll.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

- Instead of duplicating the memcpy() I'd add a single path after the
  'found' label,
- You could ensure type safety in the copy:
	
	if (pll->refcount == 0)
		pll->hw_state = crtc->config.dpll_hw_state

Oh well.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 21e20bc495ee..aef869dcc054 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3416,6 +3416,11 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
>  			      crtc->base.base.id, pll->name);
>  
> +		WARN_ON(pll->refcount);
> +
> +		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> +		       sizeof(pll->hw_state));
> +
>  		goto found;
>  	}
>  
> @@ -3442,6 +3447,10 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  		if (pll->refcount == 0) {
>  			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
>  				      crtc->base.base.id, pll->name);
> +
> +			memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> +			       sizeof(pll->hw_state));
> +
>  			goto found;
>  		}
>  	}
> @@ -3454,9 +3463,6 @@ found:
>  			 pipe_name(crtc->pipe));
>  
>  	if (pll->active == 0) {
> -		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> -		       sizeof(pll->hw_state));
> -
>  		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
>  		WARN_ON(pll->on);
>  		assert_shared_dpll_disabled(dev_priv, pll);
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 37/66] drm/i915: Extract intel_prepare_shared_dpll

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:13PM +0200, Daniel Vetter wrote:
> This is the last piece of code which write state to the hardware in
> the ironalake ->crtc_mode_set callback.
> 
> I think we could merge this with the pll->enable hook, but otoh the
> ordering requirements with the ldvs port are really tricky. Doing the
> FP0/1 writes up-front before we even prepare the lvds port (in the
> pre_pll_enable hook) like on i9xx seems safest.
> 
> With this ilk+ platforms are now ready for runtime PM with DPMS. Since
> hsw/bdw also support runtime pm besides snb we need to first make the
> haswell code save before we can touch the core code.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++++-------
>  1 file changed, 19 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index aef869dcc054..96bab640399f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1551,6 +1551,22 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  		     port_name(dport->port), I915_READ(DPLL(0)));
>  }
>  
> +static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> +
> +	WARN_ON(!pll->refcount);
> +	if (pll->active == 0) {
> +		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> +		WARN_ON(pll->on);
> +		assert_shared_dpll_disabled(dev_priv, pll);
> +
> +		pll->mode_set(dev_priv, pll);
> +	}
> +}
> +
>  /**
>   * ironlake_enable_shared_dpll - enable PCH PLL
>   * @dev_priv: i915 private structure
> @@ -3462,13 +3478,6 @@ found:
>  	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
>  			 pipe_name(crtc->pipe));
>  
> -	if (pll->active == 0) {
> -		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> -		WARN_ON(pll->on);
> -		assert_shared_dpll_disabled(dev_priv, pll);
> -
> -		pll->mode_set(dev_priv, pll);
> -	}
>  	pll->refcount++;
>  
>  	return pll;
> @@ -3699,6 +3708,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	if (intel_crtc->active)
>  		return;
>  
> +	if (intel_crtc->config.has_pch_encoder)
> +		intel_prepare_shared_dpll(intel_crtc);
> +
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 38/66] drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:14PM +0200, Daniel Vetter wrote:
> Besides the fairly useless BUG_ON the logic is completely generic
> and cane be used on any platform what wants to reuse the shared
> dpll support code.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 96bab640399f..1513d9fceebe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1568,21 +1568,19 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
>  }
>  
>  /**
> - * ironlake_enable_shared_dpll - enable PCH PLL
> + * intel_enable_shared_dpll - enable PCH PLL
>   * @dev_priv: i915 private structure
>   * @pipe: pipe PLL to enable
>   *
>   * The PCH PLL needs to be enabled before the PCH transcoder, since it
>   * drives the transcoder clock.
>   */
> -static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
> +static void intel_enable_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
>  
> -	/* PCH PLLs only available on ILK, SNB and IVB */
> -	BUG_ON(INTEL_INFO(dev)->gen < 5);
>  	if (WARN_ON(pll == NULL))
>  		return;
>  
> @@ -3328,7 +3326,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	 * Note that enable_shared_dpll tries to do the right thing, but
>  	 * get_shared_dpll unconditionally resets the pll - we need that to have
>  	 * the right LVDS enable sequence. */
> -	ironlake_enable_shared_dpll(intel_crtc);
> +	intel_enable_shared_dpll(intel_crtc);
>  
>  	/* set transcoder timing, panel must allow it */
>  	assert_panel_unlocked(dev_priv, pipe);
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 55/66] drm/i915: Add a debugfs file for the shared dpll state

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:31PM +0200, Daniel Vetter wrote:
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

The list of CRTCs using those shared PLLs would also be useful in the
mix.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 1e83ae45041c..c99951fdc572 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2370,6 +2370,31 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> +{
> +	struct drm_info_node *node = (struct drm_info_node *) m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int i;
> +
> +	drm_modeset_lock_all(dev);
> +	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> +		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
> +
> +		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
> +		seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
> +			   pll->active, yesno(pll->on));
> +		seq_printf(m, " tracked hardware state:\n");
> +		seq_printf(m, " dpll:    0x%08x\n", pll->hw_state.dpll);
> +		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
> +		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);
> +		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);
> +	}
> +	drm_modeset_unlock_all(dev);
> +
> +	return 0;
> +}
> +
>  struct pipe_crc_info {
>  	const char *name;
>  	struct drm_device *dev;
> @@ -3811,6 +3836,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_pc8_status", i915_pc8_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
> +	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
>  };
>  #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>  
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 56/66] drm/i915: Move ddi_pll_sel into the pipe config

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:32PM +0200, Daniel Vetter wrote:
> Just boring sed job for preparation.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

We want want a ddi structure to gather all the DDI config fields later
down the road.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_crt.c |  4 ++--
>  drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_drv.h |  5 +++--
>  3 files changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c4b1b1f82d01..beffae116f05 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -186,8 +186,8 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>  
>  	/* Configure Port Clock Select */
> -	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> -	WARN_ON(intel_crtc->ddi_pll_sel != PORT_CLK_SEL_SPLL);
> +	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
> +	WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
>  
>  	/* Start the training iterating through available voltages and emphasis,
>  	 * testing each value twice. */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 534cdb42e788..2adcc917806e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -262,7 +262,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	uint32_t val;
>  
> -	switch (intel_crtc->ddi_pll_sel) {
> +	switch (intel_crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  		plls->wrpll1_refcount--;
>  		if (plls->wrpll1_refcount == 0) {
> @@ -288,7 +288,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
>  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
>  
> -	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
> +	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  }
>  
>  #define LC_FREQ 2700
> @@ -623,13 +623,13 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  
>  		switch (intel_dp->link_bw) {
>  		case DP_LINK_BW_1_62:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
>  			break;
>  		case DP_LINK_BW_2_7:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
>  			break;
>  		case DP_LINK_BW_5_4:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
>  			break;
>  		default:
>  			DRM_ERROR("Link bandwidth %d unsupported\n",
> @@ -673,16 +673,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  
>  		if (reg == WRPLL_CTL1) {
>  			plls->wrpll1_refcount++;
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
>  		} else {
>  			plls->wrpll2_refcount++;
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
>  		}
>  
>  	} else if (type == INTEL_OUTPUT_ANALOG) {
>  		DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
>  			      pipe_name(pipe));
> -		intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
>  	} else {
>  		WARN(1, "Invalid DDI encoder type %d\n", type);
>  		return false;
> @@ -710,10 +710,10 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
>  	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
>  	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
>  
> -	switch (crtc->ddi_pll_sel) {
> +	switch (crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  	case PORT_CLK_SEL_WRPLL2:
> -		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
> +		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
>  			pll_name = "WRPLL1";
>  			reg = WRPLL_CTL1;
>  			refcount = plls->wrpll1_refcount;
> @@ -1035,14 +1035,14 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>  			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>  
>  		if (!intel_crtc->active) {
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  			continue;
>  		}
>  
> -		intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
> +		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
>  								 pipe);
>  
> -		switch (intel_crtc->ddi_pll_sel) {
> +		switch (intel_crtc->config.ddi_pll_sel) {
>  		case PORT_CLK_SEL_WRPLL1:
>  			dev_priv->ddi_plls.wrpll1_refcount++;
>  			break;
> @@ -1098,8 +1098,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>  		intel_edp_panel_on(intel_dp);
>  	}
>  
> -	WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
> -	I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
> +	WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
> +	I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
>  
>  	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 77414333804a..e1d079fe47ea 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -307,6 +307,9 @@ struct intel_crtc_config {
>  	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
>  	enum intel_dpll_id shared_dpll;
>  
> +	/* PORT_CLK_SEL for DDI ports. */
> +	uint32_t ddi_pll_sel;
> +
>  	/* Actual register state of the dpll, for shared dpll cross-checking. */
>  	struct intel_dpll_hw_state dpll_hw_state;
>  
> @@ -393,8 +396,6 @@ struct intel_crtc {
>  	struct intel_crtc_config *new_config;
>  	bool new_enabled;
>  
> -	uint32_t ddi_pll_sel;
> -
>  	/* reset counter value when the last flip was submitted */
>  	unsigned int reset_counter;
>  
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 57/66] drm/i915: State readout and cross-checking for ddi_pll_sel

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:33PM +0200, Daniel Vetter wrote:
> To make things a bit more manageable extract a new function for
> reading out common ddi port state. This means a bit of duplication
> between encoders and the core since both look at the same registers,
> but doesn't seem worth to make a fuzz about.
> 
> We can also remove the state readout code in intel_ddi_setup_hw_pll_state.
> That code is only called from the hardware take over and not the cross
> check code, and only after the crtc state is reconstructed. So we can
> rely on an accurate value of crtc->config.ddi_pll_sel already.
> 
> Compared to the old code also trust the hw state more and don't
> special-case port A - we want to cross-check the actual-state, not
> bake in our own assumptions about how this is supposed to all be
> linked up.
> 
> v2: Make use of the read-out ddi_pll_sel in intel_ddi_clock_get.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Moving things out of intel_ddi.c to intel_display.c seems to be the
opposite of what we want. I don't see why we couldn't leave the DDI
readout function inside intel_ddi.c?

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_ddi.c     | 40 +-----------------------------
>  drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++++++------------
>  3 files changed, 34 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 64d40f22e708..4c1cefb5f3eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5366,6 +5366,7 @@ enum punit_power_well {
>  #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
>  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
>  #define  TRANS_DDI_PORT_MASK		(7<<28)
> +#define  TRANS_DDI_PORT_SHIFT		28
>  #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
>  #define  TRANS_DDI_PORT_NONE		(0<<28)
>  #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2adcc917806e..571cfe431558 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -481,11 +481,10 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>  				struct intel_crtc_config *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> -	enum port port = intel_ddi_get_encoder_port(encoder);
>  	int link_clock = 0;
>  	u32 val, pll;
>  
> -	val = I915_READ(PORT_CLK_SEL(port));
> +	val = pipe_config->ddi_pll_sel;
>  	switch (val & PORT_CLK_SEL_MASK) {
>  	case PORT_CLK_SEL_LCPLL_810:
>  		link_clock = 81000;
> @@ -987,40 +986,6 @@ static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  	return intel_ddi_get_port_state(encoder, pipe, port);
>  }
>  
> -static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
> -				       enum pipe pipe)
> -{
> -	uint32_t temp, ret;
> -	enum port port = I915_MAX_PORTS;
> -	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
> -								      pipe);
> -	int i;
> -
> -	if (cpu_transcoder == TRANSCODER_EDP) {
> -		port = PORT_A;
> -	} else {
> -		temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> -		temp &= TRANS_DDI_PORT_MASK;
> -
> -		for (i = PORT_B; i <= PORT_E; i++)
> -			if (temp == TRANS_DDI_SELECT_PORT(i))
> -				port = i;
> -	}
> -
> -	if (port == I915_MAX_PORTS) {
> -		WARN(1, "Pipe %c enabled on an unknown port\n",
> -		     pipe_name(pipe));
> -		ret = PORT_CLK_SEL_NONE;
> -	} else {
> -		ret = I915_READ(PORT_CLK_SEL(port));
> -		DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
> -			      "0x%08x\n", pipe_name(pipe), port_name(port),
> -			      ret);
> -	}
> -
> -	return ret;
> -}
> -
>  void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1039,9 +1004,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>  			continue;
>  		}
>  
> -		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
> -								 pipe);
> -
>  		switch (intel_crtc->config.ddi_pll_sel) {
>  		case PORT_CLK_SEL_WRPLL1:
>  			dev_priv->ddi_plls.wrpll1_refcount++;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 728b5a25cb80..1601da1b57a1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7006,6 +7006,35 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>  	return 0;
>  }
>  
> +static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> +				       struct intel_crtc_config *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum port port;
> +	uint32_t tmp;
> +
> +	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> +
> +	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
> +
> +	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
> +	/*
> +	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
> +	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> +	 * the PCH transcoder is on.
> +	 */
> +	if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> +		pipe_config->has_pch_encoder = true;
> +
> +		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> +		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> +					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> +
> +		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> +	}
> +}
> +
>  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  				    struct intel_crtc_config *pipe_config)
>  {
> @@ -7051,22 +7080,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> -	/*
> -	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
> -	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> -	 * the PCH transcoder is on.
> -	 */
> -	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> -	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
> -	    I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> -		pipe_config->has_pch_encoder = true;
> -
> -		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> -		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> -					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> -
> -		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> -	}
> +	haswell_get_ddi_port_state(crtc, pipe_config);
>  
>  	intel_get_pipe_timings(crtc, pipe_config);
>  
> @@ -9521,6 +9535,8 @@ intel_pipe_config_compare(struct drm_device *dev,
>  
>  	PIPE_CONF_CHECK_I(double_wide);
>  
> +	PIPE_CONF_CHECK_X(ddi_pll_sel);
> +
>  	PIPE_CONF_CHECK_I(shared_dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 58/66] drm/i915: Precompute static ddi_pll_sel values in encoders

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:34PM +0200, Daniel Vetter wrote:
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
>  			POSTING_READ(WRPLL_CTL1);
>  		}
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
>  	case PORT_CLK_SEL_WRPLL2:
>  		plls->wrpll2_refcount--;
> @@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
>  			POSTING_READ(WRPLL_CTL2);
>  		}
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
>  	}
>  
>  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
>  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
> -
> -	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  }

Who sets config.ddi_pll_sel to NONE for VGA and DP now?

-- 
Damien

Re: [PATCH 59/66] drm/i915: Basic shared dpll support for WRPLLs

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:35PM +0200, Daniel Vetter wrote:
> Just filing in names and ids, but not yet officially registering them
> so that the hw state cross checker doesn't completely freak out about
> them. Still since we do already read out and cross check
> config->shared_dpll the basics are now there to flesh out the wrpll
> shared dpll implementation.
> 
> The idea is now to roll out all the callbacks step-by-step and then at
> the end switch to the shared dpll framework. This way hw and sw
> changes are clearly separated.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

With the consts added:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  6 ++++--
>  drivers/gpu/drm/i915/intel_ddi.c     | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++--------
>  3 files changed, 34 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b6eac92e0a22..babeb7e92ee4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -176,8 +176,10 @@ struct drm_i915_private;
>  enum intel_dpll_id {
>  	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
>  	/* real shared dpll ids must be >= 0 */
> -	DPLL_ID_PCH_PLL_A,
> -	DPLL_ID_PCH_PLL_B,
> +	DPLL_ID_PCH_PLL_A = 0,
> +	DPLL_ID_PCH_PLL_B = 1,
> +	DPLL_ID_WRPLL1 = 0,
> +	DPLL_ID_WRPLL2 = 1,
>  };
>  #define I915_NUM_PLLS 2
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cc03f0af517b..8316e0e624a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -653,9 +653,11 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  		if (reg == WRPLL_CTL1) {
>  			plls->wrpll1_refcount++;
>  			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
> +			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
>  		} else {
>  			plls->wrpll2_refcount++;
>  			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> +			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
>  		}
>  	}
>  
> @@ -1183,10 +1185,25 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static char *hsw_ddi_pll_names[] = {
> +	"WRPLL 1",
> +	"WRPLL 2",
> +};
> +

static const char * const

>  void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t val = I915_READ(LCPLL_CTL);
> +	int i;
> +
> +	/* Dummy setup until everything is moved over to avoid upsetting the hw
> +	 * state cross checker. */
> +	dev_priv->num_shared_dpll = 0;
> +
> +	for (i = 0; i < 2; i++) {
> +		dev_priv->shared_dplls[i].id = i;
> +		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
> +	}
>  
>  	/* The LCPLL register should be turned on by the BIOS. For now let's
>  	 * just check its state and print errors in case something is wrong.
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1601da1b57a1..fc7cd89b8921 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7019,6 +7019,16 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>  
>  	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
> +
> +	switch (pipe_config->ddi_pll_sel) {
> +	case PORT_CLK_SEL_WRPLL1:
> +		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
> +		break;
> +	case PORT_CLK_SEL_WRPLL2:
> +		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
> +		break;
> +	}
> +
>  	/*
>  	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
>  	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> @@ -10340,12 +10350,6 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
>  	.page_flip = intel_crtc_page_flip,
>  };
>  
> -static void intel_cpu_pll_init(struct drm_device *dev)
> -{
> -	if (HAS_DDI(dev))
> -		intel_ddi_pll_init(dev);
> -}
> -
>  static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  				      struct intel_shared_dpll *pll,
>  				      struct intel_dpll_hw_state *hw_state)
> @@ -10433,7 +10437,9 @@ static void intel_shared_dpll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	if (HAS_DDI(dev))
> +		intel_ddi_pll_init(dev);
> +	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>  		ibx_pch_dpll_init(dev);
>  	else
>  		dev_priv->num_shared_dpll = 0;
> @@ -11232,7 +11238,6 @@ void intel_modeset_init(struct drm_device *dev)
>  	intel_init_dpio(dev);
>  	intel_reset_dpio(dev);
>  
> -	intel_cpu_pll_init(dev);
>  	intel_shared_dpll_init(dev);
>  
>  	/* Just disable it once at startup */
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 60/66] drm/i915: Document that the pll->mode_set hook is optional

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:36PM +0200, Daniel Vetter wrote:
> The WRPLLs won't use them.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

/*
 * Comments spawning multiple lines are formatted...
 * ...this way
 */

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index babeb7e92ee4..b01ee265310f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -198,6 +198,8 @@ struct intel_shared_dpll {
>  	/* should match the index in the dev_priv->shared_dplls array */
>  	enum intel_dpll_id id;
>  	struct intel_dpll_hw_state hw_state;
> +	/* The mode_set hook is optional and should be used together with the
> +	 * intel_prepare_shared_dpll function. */
>  	void (*mode_set)(struct drm_i915_private *dev_priv,
>  			 struct intel_shared_dpll *pll);
>  	void (*enable)(struct drm_i915_private *dev_priv,
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 61/66] drm/i915: State readout support for WRPLLs

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:37PM +0200, Daniel Vetter wrote:
> Still tacked onto the side, but slowly getting there.
> 
> v2: Don't forget the debugfs file.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |  1 +
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_ddi.c     | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |  9 +++++++++
>  5 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c99951fdc572..a579685348aa 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2389,6 +2389,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
>  		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);
>  		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);
> +		seq_printf(m, " wrpll:   0x%08x\n", pll->hw_state.wrpll);
>  	}
>  	drm_modeset_unlock_all(dev);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b01ee265310f..bebc507f776b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -188,6 +188,7 @@ struct intel_dpll_hw_state {
>  	uint32_t dpll_md;
>  	uint32_t fp0;
>  	uint32_t fp1;
> +	uint32_t wrpll;
>  };
>  
>  struct intel_shared_dpll {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4c1cefb5f3eb..99051e6348b8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5505,6 +5505,7 @@ enum punit_power_well {
>  /* WRPLL */
>  #define WRPLL_CTL1			0x46040
>  #define WRPLL_CTL2			0x46060
> +#define WRPLL_CTL(pll)			(pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
>  #define  WRPLL_PLL_ENABLE		(1<<31)
>  #define  WRPLL_PLL_SSC			(1<<28)
>  #define  WRPLL_PLL_NON_SSC		(2<<28)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8316e0e624a4..73875ee4bb68 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -659,6 +659,8 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
>  			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
>  		}
> +
> +		intel_crtc->config.dpll_hw_state.wrpll = val;
>  	}
>  
>  	return true;
> @@ -1185,6 +1187,18 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> +				     struct intel_shared_dpll *pll,
> +				     struct intel_dpll_hw_state *hw_state)
> +{
> +	uint32_t val;
> +
> +	val = I915_READ(WRPLL_CTL(pll->id));
> +	hw_state->wrpll = val;
> +
> +	return val & WRPLL_PLL_ENABLE;
> +}
> +
>  static char *hsw_ddi_pll_names[] = {
>  	"WRPLL 1",
>  	"WRPLL 2",
> @@ -1203,6 +1217,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	for (i = 0; i < 2; i++) {
>  		dev_priv->shared_dplls[i].id = i;
>  		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
> +		dev_priv->shared_dplls[i].get_hw_state =
> +			hsw_ddi_pll_get_hw_state;
>  	}
>  
>  	/* The LCPLL register should be turned on by the BIOS. For now let's
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fc7cd89b8921..b5086fd83596 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7011,6 +7011,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_shared_dpll *pll;
>  	enum port port;
>  	uint32_t tmp;
>  
> @@ -7029,6 +7030,13 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  		break;
>  	}
>  
> +	if (pipe_config->shared_dpll >= 0) {
> +		pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
> +
> +		WARN_ON(!pll->get_hw_state(dev_priv, pll,
> +					   &pipe_config->dpll_hw_state));
> +	}
> +
>  	/*
>  	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
>  	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> @@ -9552,6 +9560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
>  
>  	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
>  		PIPE_CONF_CHECK_I(pipe_bpp);
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 36/66] drm/i915: Only update shared dpll state when needed

[Daniel Vetter]

On Tue, May 20, 2014 at 11:18:54AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:12PM +0200, Daniel Vetter wrote:
> > Instead of every time it isn't active: We only need to do that when
> > the pll is currently unused, i.e. when pll->refcount == 0. For
> > paranoia add a warning for the ibx case where plls have a fixed
> > mapping and hence should always be unused after the call to
> > intel_put_shared_dpll.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> - Instead of duplicating the memcpy() I'd add a single path after the
>   'found' label,
> - You could ensure type safety in the copy:
> 	
> 	if (pll->refcount == 0)
> 		pll->hw_state = crtc->config.dpll_hw_state

I like this, so will quickly respin.
-Daniel

> 
> Oh well.
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 12 +++++++++---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 21e20bc495ee..aef869dcc054 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3416,6 +3416,11 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
> >  		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
> >  			      crtc->base.base.id, pll->name);
> >  
> > +		WARN_ON(pll->refcount);
> > +
> > +		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> > +		       sizeof(pll->hw_state));
> > +
> >  		goto found;
> >  	}
> >  
> > @@ -3442,6 +3447,10 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
> >  		if (pll->refcount == 0) {
> >  			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
> >  				      crtc->base.base.id, pll->name);
> > +
> > +			memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> > +			       sizeof(pll->hw_state));
> > +
> >  			goto found;
> >  		}
> >  	}
> > @@ -3454,9 +3463,6 @@ found:
> >  			 pipe_name(crtc->pipe));
> >  
> >  	if (pll->active == 0) {
> > -		memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
> > -		       sizeof(pll->hw_state));
> > -
> >  		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> >  		WARN_ON(pll->on);
> >  		assert_shared_dpll_disabled(dev_priv, pll);
> > -- 
> > 1.8.1.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 62/66] drm/i915: ->disable hook for WRPLLs

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:38PM +0200, Daniel Vetter wrote:
> Currently still with a redudant WARN_ON in there, the common shared
> dpll code will take care of this in the future.
> 
> Also we need to flip the switch for the transitional hack now to make
> sure that we disable the right pll.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

With the small bikeshed below:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 27 ++++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_display.c |  8 +++++---
>  2 files changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 73875ee4bb68..e7e1a84fe453 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -260,28 +260,21 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
>  	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	uint32_t val;
> +
> +	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(intel_crtc);

Spurious new line.

>  	switch (intel_crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  		plls->wrpll1_refcount--;
>  		if (plls->wrpll1_refcount == 0) {
> -			DRM_DEBUG_KMS("Disabling WRPLL 1\n");
> -			val = I915_READ(WRPLL_CTL1);
> -			WARN_ON(!(val & WRPLL_PLL_ENABLE));
> -			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
> -			POSTING_READ(WRPLL_CTL1);
> +			pll->disable(dev_priv, pll);
>  		}
>  		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
>  	case PORT_CLK_SEL_WRPLL2:
>  		plls->wrpll2_refcount--;
>  		if (plls->wrpll2_refcount == 0) {
> -			DRM_DEBUG_KMS("Disabling WRPLL 2\n");
> -			val = I915_READ(WRPLL_CTL2);
> -			WARN_ON(!(val & WRPLL_PLL_ENABLE));
> -			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
> -			POSTING_READ(WRPLL_CTL2);
> +			pll->disable(dev_priv, pll);
>  		}
>  		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
> @@ -1187,6 +1180,17 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
> +				struct intel_shared_dpll *pll)
> +{
> +	uint32_t val;
> +
> +	val = I915_READ(WRPLL_CTL(pll->id));
> +	WARN_ON(!(val & WRPLL_PLL_ENABLE));
> +	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
> +	POSTING_READ(WRPLL_CTL(pll->id));
> +}
> +
>  static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  				     struct intel_shared_dpll *pll,
>  				     struct intel_dpll_hw_state *hw_state)
> @@ -1217,6 +1221,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	for (i = 0; i < 2; i++) {
>  		dev_priv->shared_dplls[i].id = i;
>  		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
> +		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
>  		dev_priv->shared_dplls[i].get_hw_state =
>  			hsw_ddi_pll_get_hw_state;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b5086fd83596..b890c97f1312 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4788,9 +4788,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  	if (HAS_IPS(dev))
>  		hsw_compute_ips_config(crtc, pipe_config);
>  
> -	/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
> -	 * clock survives for now. */
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	/*
> +	 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
> +	 * old clock survives for now.
> +	 */
> +	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
>  		pipe_config->shared_dpll = crtc->config.shared_dpll;
>  
>  	if (pipe_config->has_pch_encoder)
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 57/66] drm/i915: State readout and cross-checking for ddi_pll_sel

[Daniel Vetter]

On Tue, May 20, 2014 at 11:47:35AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:33PM +0200, Daniel Vetter wrote:
> > To make things a bit more manageable extract a new function for
> > reading out common ddi port state. This means a bit of duplication
> > between encoders and the core since both look at the same registers,
> > but doesn't seem worth to make a fuzz about.
> > 
> > We can also remove the state readout code in intel_ddi_setup_hw_pll_state.
> > That code is only called from the hardware take over and not the cross
> > check code, and only after the crtc state is reconstructed. So we can
> > rely on an accurate value of crtc->config.ddi_pll_sel already.
> > 
> > Compared to the old code also trust the hw state more and don't
> > special-case port A - we want to cross-check the actual-state, not
> > bake in our own assumptions about how this is supposed to all be
> > linked up.
> > 
> > v2: Make use of the read-out ddi_pll_sel in intel_ddi_clock_get.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Moving things out of intel_ddi.c to intel_display.c seems to be the
> opposite of what we want. I don't see why we couldn't leave the DDI
> readout function inside intel_ddi.c?

Fewer forward decls and non-static functions. If you have a file with a
bunch of functions but they're all called from somewhere else, then the
split-up is imo not functionally sound. intel_ddi.c has a bit that taste
for me.

We could fix this I guess by moving a lot more into intel_ddi.c, like all
the hsw+ modeset code.

> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  1 +
> >  drivers/gpu/drm/i915/intel_ddi.c     | 40 +-----------------------------
> >  drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++++++------------
> >  3 files changed, 34 insertions(+), 55 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 64d40f22e708..4c1cefb5f3eb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5366,6 +5366,7 @@ enum punit_power_well {
> >  #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
> >  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> >  #define  TRANS_DDI_PORT_MASK		(7<<28)
> > +#define  TRANS_DDI_PORT_SHIFT		28
> >  #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
> >  #define  TRANS_DDI_PORT_NONE		(0<<28)
> >  #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 2adcc917806e..571cfe431558 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -481,11 +481,10 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> >  				struct intel_crtc_config *pipe_config)
> >  {
> >  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> > -	enum port port = intel_ddi_get_encoder_port(encoder);
> >  	int link_clock = 0;
> >  	u32 val, pll;
> >  
> > -	val = I915_READ(PORT_CLK_SEL(port));
> > +	val = pipe_config->ddi_pll_sel;
> >  	switch (val & PORT_CLK_SEL_MASK) {
> >  	case PORT_CLK_SEL_LCPLL_810:
> >  		link_clock = 81000;
> > @@ -987,40 +986,6 @@ static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> >  	return intel_ddi_get_port_state(encoder, pipe, port);
> >  }
> >  
> > -static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
> > -				       enum pipe pipe)
> > -{
> > -	uint32_t temp, ret;
> > -	enum port port = I915_MAX_PORTS;
> > -	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
> > -								      pipe);
> > -	int i;
> > -
> > -	if (cpu_transcoder == TRANSCODER_EDP) {
> > -		port = PORT_A;
> > -	} else {
> > -		temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > -		temp &= TRANS_DDI_PORT_MASK;
> > -
> > -		for (i = PORT_B; i <= PORT_E; i++)
> > -			if (temp == TRANS_DDI_SELECT_PORT(i))
> > -				port = i;
> > -	}
> > -
> > -	if (port == I915_MAX_PORTS) {
> > -		WARN(1, "Pipe %c enabled on an unknown port\n",
> > -		     pipe_name(pipe));
> > -		ret = PORT_CLK_SEL_NONE;
> > -	} else {
> > -		ret = I915_READ(PORT_CLK_SEL(port));
> > -		DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
> > -			      "0x%08x\n", pipe_name(pipe), port_name(port),
> > -			      ret);
> > -	}
> > -
> > -	return ret;
> > -}
> > -
> >  void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -1039,9 +1004,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
> >  			continue;
> >  		}
> >  
> > -		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
> > -								 pipe);
> > -
> >  		switch (intel_crtc->config.ddi_pll_sel) {
> >  		case PORT_CLK_SEL_WRPLL1:
> >  			dev_priv->ddi_plls.wrpll1_refcount++;
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 728b5a25cb80..1601da1b57a1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7006,6 +7006,35 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> >  	return 0;
> >  }
> >  
> > +static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> > +				       struct intel_crtc_config *pipe_config)
> > +{
> > +	struct drm_device *dev = crtc->base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	enum port port;
> > +	uint32_t tmp;
> > +
> > +	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> > +
> > +	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
> > +
> > +	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
> > +	/*
> > +	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
> > +	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> > +	 * the PCH transcoder is on.
> > +	 */
> > +	if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> > +		pipe_config->has_pch_encoder = true;
> > +
> > +		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> > +		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> > +					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> > +
> > +		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> > +	}
> > +}
> > +
> >  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> >  				    struct intel_crtc_config *pipe_config)
> >  {
> > @@ -7051,22 +7080,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> >  	if (!(tmp & PIPECONF_ENABLE))
> >  		return false;
> >  
> > -	/*
> > -	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
> > -	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> > -	 * the PCH transcoder is on.
> > -	 */
> > -	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> > -	if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
> > -	    I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
> > -		pipe_config->has_pch_encoder = true;
> > -
> > -		tmp = I915_READ(FDI_RX_CTL(PIPE_A));
> > -		pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
> > -					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> > -
> > -		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> > -	}
> > +	haswell_get_ddi_port_state(crtc, pipe_config);
> >  
> >  	intel_get_pipe_timings(crtc, pipe_config);
> >  
> > @@ -9521,6 +9535,8 @@ intel_pipe_config_compare(struct drm_device *dev,
> >  
> >  	PIPE_CONF_CHECK_I(double_wide);
> >  
> > +	PIPE_CONF_CHECK_X(ddi_pll_sel);
> > +
> >  	PIPE_CONF_CHECK_I(shared_dpll);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> >  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> > -- 
> > 1.8.1.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 58/66] drm/i915: Precompute static ddi_pll_sel values in encoders

[Daniel Vetter]

On Tue, May 20, 2014 at 11:56:28AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:34PM +0200, Daniel Vetter wrote:
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> >  			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
> >  			POSTING_READ(WRPLL_CTL1);
> >  		}
> > +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL2:
> >  		plls->wrpll2_refcount--;
> > @@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> >  			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
> >  			POSTING_READ(WRPLL_CTL2);
> >  		}
> > +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  		break;
> >  	}
> >  
> >  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
> >  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
> > -
> > -	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  }
> 
> Who sets config.ddi_pll_sel to NONE for VGA and DP now?

We don't care about that any more. The spll handling was completely moved
into intel_crt.c with the intermediate patches, and intel DP directly keys
off the right clock from config->port_clock.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 63/66] drm/i915: ->enable hook for WRPLLs

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:39PM +0200, Daniel Vetter wrote:
> This time around another cute hack to pre-fill the pll->hw_state with
> the right values. And also remove a bunch of checks which will be
> replaced by lots more checks in the common framework.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 51 +++++++++++++++-------------------------
>  1 file changed, 19 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index e7e1a84fe453..21e451ea0c69 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -610,6 +610,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  	intel_ddi_put_crtc_pll(crtc);
>  
>  	if (type == INTEL_OUTPUT_HDMI) {
> +		struct intel_shared_dpll *pll;
>  		uint32_t reg, val;
>  		unsigned p, n2, r2;
>  
> @@ -654,6 +655,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  		}
>  
>  		intel_crtc->config.dpll_hw_state.wrpll = val;
> +
> +		pll = &dev_priv->shared_dplls[intel_crtc->config.shared_dpll];
> +		pll->hw_state.wrpll = val;
>  	}
>  
>  	return true;
> @@ -668,54 +672,24 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
> -	int clock = crtc->config.port_clock;
> -	uint32_t reg, cur_val, new_val;
>  	int refcount;
> -	const char *pll_name;
> -	uint32_t enable_bit = (1 << 31);
> -	unsigned int p, n2, r2;
> -
> -	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
> -	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
> +	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
>  
>  	switch (crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  	case PORT_CLK_SEL_WRPLL2:
>  		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
> -			pll_name = "WRPLL1";
> -			reg = WRPLL_CTL1;
>  			refcount = plls->wrpll1_refcount;
>  		} else {
> -			pll_name = "WRPLL2";
> -			reg = WRPLL_CTL2;
>  			refcount = plls->wrpll2_refcount;
>  		}
> -
> -		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
> -
> -		new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
> -			  WRPLL_DIVIDER_REFERENCE(r2) |
> -			  WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
> -
>  		break;
> -
> -	case PORT_CLK_SEL_NONE:
> -		WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
> -		return;
>  	default:
>  		return;
>  	}
>  
> -	cur_val = I915_READ(reg);
> -
> -	WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
>  	if (refcount == 1) {
> -		WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
> -		I915_WRITE(reg, new_val);
> -		POSTING_READ(reg);
> -		udelay(20);
> -	} else {
> -		WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
> +		pll->enable(dev_priv, pll);
>  	}
>  }
>  
> @@ -1180,6 +1154,18 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
> +			       struct intel_shared_dpll *pll)
> +{
> +	uint32_t cur_val;
> +
> +	cur_val = I915_READ(WRPLL_CTL(pll->id));
> +	WARN(cur_val & WRPLL_PLL_ENABLE, "%s already enabled\n", pll->name);
> +	I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
> +	POSTING_READ(WRPLL_CTL(pll->id));
> +	udelay(20);
> +}
> +
>  static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
> @@ -1222,6 +1208,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  		dev_priv->shared_dplls[i].id = i;
>  		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
>  		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
> +		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
>  		dev_priv->shared_dplls[i].get_hw_state =
>  			hsw_ddi_pll_get_hw_state;
>  	}
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 64/66] drm/i915: Switch to common shared dpll framework for WRPLLs

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:40PM +0200, Daniel Vetter wrote:
> Mostly this patch is one big excersize in deleting code and asserts
> which are no longer needed. Note that we still abuse the shared dpll
> framework a bit since we call the enable/disable functions from the
> crtc mode_set and off hooks. But changing the actual hardware sequence
> will be done in the next step.
> 
> Note that besides the massive amount of changes in this patch the
> places and order in which the low-level WRPLL code is called is
> absolutely unchanged.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   6 --
>  drivers/gpu/drm/i915/i915_reg.h      |   1 +
>  drivers/gpu/drm/i915/intel_ddi.c     | 142 ++++-------------------------------
>  drivers/gpu/drm/i915/intel_display.c |  14 ++--
>  drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
>  5 files changed, 27 insertions(+), 145 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bebc507f776b..73371161777b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -225,11 +225,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n);
>  
> -struct intel_ddi_plls {
> -	int wrpll1_refcount;
> -	int wrpll2_refcount;
> -};
> -
>  /* Interface history:
>   *
>   * 1.1: Original.
> @@ -1399,7 +1394,6 @@ struct drm_i915_private {
>  
>  	int num_shared_dpll;
>  	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> -	struct intel_ddi_plls ddi_plls;
>  	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
>  
>  	/* Reclocking support */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 99051e6348b8..fcb1ca6eadb5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5529,6 +5529,7 @@ enum punit_power_well {
>  #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
>  #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
>  #define  PORT_CLK_SEL_SPLL		(3<<29)
> +#define  PORT_CLK_SEL_WRPLL(pll)	(((pll)+4)<<29)
>  #define  PORT_CLK_SEL_WRPLL1		(4<<29)
>  #define  PORT_CLK_SEL_WRPLL2		(5<<29)
>  #define  PORT_CLK_SEL_NONE		(7<<29)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 21e451ea0c69..7386a1212e71 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -257,31 +257,12 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
>  
>  void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> -	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  
> -	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(intel_crtc);
> -
> -	switch (intel_crtc->config.ddi_pll_sel) {
> -	case PORT_CLK_SEL_WRPLL1:
> -		plls->wrpll1_refcount--;
> -		if (plls->wrpll1_refcount == 0) {
> -			pll->disable(dev_priv, pll);
> -		}
> -		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> -		break;
> -	case PORT_CLK_SEL_WRPLL2:
> -		plls->wrpll2_refcount--;
> -		if (plls->wrpll2_refcount == 0) {
> -			pll->disable(dev_priv, pll);
> -		}
> -		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> -		break;
> -	}
> +	if (intel_crtc_to_shared_dpll(intel_crtc))
> +		intel_disable_shared_dpll(intel_crtc);
>  
> -	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
> -	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
> +	intel_put_shared_dpll(intel_crtc);
>  }
>  
>  #define LC_FREQ 2700
> @@ -601,17 +582,14 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_crtc *crtc = &intel_crtc->base;
>  	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> -	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> -	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
>  	int type = intel_encoder->type;
> -	enum pipe pipe = intel_crtc->pipe;
>  	int clock = intel_crtc->config.port_clock;
>  
>  	intel_ddi_put_crtc_pll(crtc);
>  
>  	if (type == INTEL_OUTPUT_HDMI) {
>  		struct intel_shared_dpll *pll;
> -		uint32_t reg, val;
> +		uint32_t val;
>  		unsigned p, n2, r2;
>  
>  		intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
> @@ -620,79 +598,21 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>  		      WRPLL_DIVIDER_POST(p);
>  
> -		if (val == I915_READ(WRPLL_CTL1)) {
> -			DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
> -				      pipe_name(pipe));
> -			reg = WRPLL_CTL1;
> -		} else if (val == I915_READ(WRPLL_CTL2)) {
> -			DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
> -				      pipe_name(pipe));
> -			reg = WRPLL_CTL2;
> -		} else if (plls->wrpll1_refcount == 0) {
> -			DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
> -				      pipe_name(pipe));
> -			reg = WRPLL_CTL1;
> -		} else if (plls->wrpll2_refcount == 0) {
> -			DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
> -				      pipe_name(pipe));
> -			reg = WRPLL_CTL2;
> -		} else {
> -			DRM_ERROR("No WRPLLs available!\n");
> -			return false;
> -		}
> +		intel_crtc->config.dpll_hw_state.wrpll = val;
>  
> -		DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
> -			      clock, p, n2, r2);
> -
> -		if (reg == WRPLL_CTL1) {
> -			plls->wrpll1_refcount++;
> -			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
> -			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
> -		} else {
> -			plls->wrpll2_refcount++;
> -			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> -			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
> +		pll = intel_get_shared_dpll(intel_crtc);
> +		if (pll == NULL) {
> +			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
> +					 pipe_name(intel_crtc->pipe));
> +			return false;
>  		}
>  
> -		intel_crtc->config.dpll_hw_state.wrpll = val;
> -
> -		pll = &dev_priv->shared_dplls[intel_crtc->config.shared_dpll];
> -		pll->hw_state.wrpll = val;
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
>  	}
>  
>  	return true;
>  }
>  
> -/*
> - * To be called after intel_ddi_pll_select(). That one selects the PLL to be
> - * used, this one actually enables the PLL.
> - */
> -void intel_ddi_pll_enable(struct intel_crtc *crtc)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
> -	int refcount;
> -	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> -
> -	switch (crtc->config.ddi_pll_sel) {
> -	case PORT_CLK_SEL_WRPLL1:
> -	case PORT_CLK_SEL_WRPLL2:
> -		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
> -			refcount = plls->wrpll1_refcount;
> -		} else {
> -			refcount = plls->wrpll2_refcount;
> -		}
> -		break;
> -	default:
> -		return;
> -	}
> -
> -	if (refcount == 1) {
> -		pll->enable(dev_priv, pll);
> -	}
> -}
> -
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> @@ -929,35 +849,6 @@ static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  	return intel_ddi_get_port_state(encoder, pipe, port);
>  }
>  
> -void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	enum pipe pipe;
> -	struct intel_crtc *intel_crtc;
> -
> -	dev_priv->ddi_plls.wrpll1_refcount = 0;
> -	dev_priv->ddi_plls.wrpll2_refcount = 0;
> -
> -	for_each_pipe(pipe) {
> -		intel_crtc =
> -			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
> -
> -		if (!intel_crtc->active) {
> -			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> -			continue;
> -		}
> -
> -		switch (intel_crtc->config.ddi_pll_sel) {
> -		case PORT_CLK_SEL_WRPLL1:
> -			dev_priv->ddi_plls.wrpll1_refcount++;
> -			break;
> -		case PORT_CLK_SEL_WRPLL2:
> -			dev_priv->ddi_plls.wrpll2_refcount++;
> -			break;
> -		}
> -	}
> -}
> -
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_crtc *crtc = &intel_crtc->base;
> @@ -1157,10 +1048,6 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll)
>  {
> -	uint32_t cur_val;
> -
> -	cur_val = I915_READ(WRPLL_CTL(pll->id));
> -	WARN(cur_val & WRPLL_PLL_ENABLE, "%s already enabled\n", pll->name);
>  	I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
>  	POSTING_READ(WRPLL_CTL(pll->id));
>  	udelay(20);
> @@ -1172,7 +1059,6 @@ static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	uint32_t val;
>  
>  	val = I915_READ(WRPLL_CTL(pll->id));
> -	WARN_ON(!(val & WRPLL_PLL_ENABLE));
>  	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
>  	POSTING_READ(WRPLL_CTL(pll->id));
>  }
> @@ -1200,11 +1086,9 @@ void intel_ddi_pll_init(struct drm_device *dev)
>  	uint32_t val = I915_READ(LCPLL_CTL);
>  	int i;
>  
> -	/* Dummy setup until everything is moved over to avoid upsetting the hw
> -	 * state cross checker. */
> -	dev_priv->num_shared_dpll = 0;
> +	dev_priv->num_shared_dpll = 2;
>  
> -	for (i = 0; i < 2; i++) {
> +	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		dev_priv->shared_dplls[i].id = i;
>  		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
>  		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b890c97f1312..2fd77eba57f3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1599,7 +1599,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
>  	pll->on = true;
>  }
>  
> -static void intel_disable_shared_dpll(struct intel_crtc *crtc)
> +void intel_disable_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3232,7 +3232,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	ironlake_enable_pch_transcoder(dev_priv, pipe);
>  }
>  
> -static void intel_put_shared_dpll(struct intel_crtc *crtc)
> +void intel_put_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
>  
> @@ -3252,7 +3252,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
>  	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
>  }
>  
> -static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
> +struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> @@ -7001,7 +7001,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	if (!intel_ddi_pll_select(intel_crtc))
>  		return -EINVAL;
> -	intel_ddi_pll_enable(intel_crtc);
> +
> +	if (intel_crtc_to_shared_dpll(intel_crtc))
> +		intel_enable_shared_dpll(intel_crtc);
>  
>  	intel_crtc->lowfreq_avail = false;
>  
> @@ -11531,10 +11533,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			      crtc->active ? "enabled" : "disabled");
>  	}
>  
> -	/* FIXME: Smash this into the new shared dpll infrastructure. */
> -	if (HAS_DDI(dev))
> -		intel_ddi_setup_hw_pll_state(dev);
> -
>  	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>  		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e1d079fe47ea..acd32e8e5e13 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -682,9 +682,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  				       enum transcoder cpu_transcoder);
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
>  void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
> -void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
>  bool intel_ddi_pll_select(struct intel_crtc *crtc);
> -void intel_ddi_pll_enable(struct intel_crtc *crtc);
>  void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
>  void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
> @@ -740,12 +738,19 @@ __intel_framebuffer_create(struct drm_device *dev,
>  void intel_prepare_page_flip(struct drm_device *dev, int plane);
>  void intel_finish_page_flip(struct drm_device *dev, int pipe);
>  void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
> +
> +/* shared dpll functions */
>  struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
>  void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			struct intel_shared_dpll *pll,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +void intel_disable_shared_dpll(struct intel_crtc *crtc);
> +struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
> +void intel_put_shared_dpll(struct intel_crtc *crtc);
> +
> +/* modesetting asserts */
>  void assert_pll(struct drm_i915_private *dev_priv,
>  		enum pipe pipe, bool state);
>  #define assert_pll_enabled(d, p) assert_pll(d, p, true)
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 65/66] drm/i915: Only touch WRPLL hw state in enable/disable hooks

[Damien Lespiau]

On Thu, Apr 24, 2014 at 11:55:41PM +0200, Daniel Vetter wrote:
> To be able to do this we need to separately keep track of how many
> crtcs need a given WRPLL and how many actually actively use it. The
> common shared dpll framework already has all this, including massive
> state readout and cross checking. Which allows us to do this switch in
> a fairly small patch.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 12 +-----------
>  drivers/gpu/drm/i915/intel_display.c | 16 +++++++---------
>  drivers/gpu/drm/i915/intel_drv.h     |  2 --
>  3 files changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7386a1212e71..97f9cd6dbee1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -255,16 +255,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
>  	return ret;
>  }
>  
> -void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> -{
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> -	if (intel_crtc_to_shared_dpll(intel_crtc))
> -		intel_disable_shared_dpll(intel_crtc);
> -
> -	intel_put_shared_dpll(intel_crtc);
> -}
> -
>  #define LC_FREQ 2700
>  #define LC_FREQ_2K (LC_FREQ * 2000)
>  
> @@ -585,7 +575,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  	int type = intel_encoder->type;
>  	int clock = intel_crtc->config.port_clock;
>  
> -	intel_ddi_put_crtc_pll(crtc);
> +	intel_put_shared_dpll(intel_crtc);
>  
>  	if (type == INTEL_OUTPUT_HDMI) {
>  		struct intel_shared_dpll *pll;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2fd77eba57f3..e0bd0f94e43e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3673,6 +3673,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	if (intel_crtc->active)
>  		return;
>  
> +	if (intel_crtc_to_shared_dpll(intel_crtc))
> +		intel_enable_shared_dpll(intel_crtc);
> +
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
> @@ -3846,6 +3849,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	intel_update_fbc(dev);
>  	intel_edp_psr_update(dev);
>  	mutex_unlock(&dev->struct_mutex);
> +
> +	if (intel_crtc_to_shared_dpll(intel_crtc))
> +		intel_disable_shared_dpll(intel_crtc);
>  }
>  
>  static void ironlake_crtc_off(struct drm_crtc *crtc)
> @@ -3854,11 +3860,6 @@ static void ironlake_crtc_off(struct drm_crtc *crtc)
>  	intel_put_shared_dpll(intel_crtc);
>  }
>  
> -static void haswell_crtc_off(struct drm_crtc *crtc)
> -{
> -	intel_ddi_put_crtc_pll(crtc);
> -}
> -
>  static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
>  {
>  	if (!enable && intel_crtc->overlay) {
> @@ -7002,9 +7003,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>  	if (!intel_ddi_pll_select(intel_crtc))
>  		return -EINVAL;
>  
> -	if (intel_crtc_to_shared_dpll(intel_crtc))
> -		intel_enable_shared_dpll(intel_crtc);
> -
>  	intel_crtc->lowfreq_avail = false;
>  
>  	return 0;
> @@ -10904,7 +10902,7 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
>  		dev_priv->display.crtc_enable = haswell_crtc_enable;
>  		dev_priv->display.crtc_disable = haswell_crtc_disable;
> -		dev_priv->display.off = haswell_crtc_off;
> +		dev_priv->display.off = ironlake_crtc_off;
>  		dev_priv->display.update_primary_plane =
>  			ironlake_update_primary_plane;
>  	} else if (HAS_PCH_SPLIT(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index acd32e8e5e13..81a7813fc78b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -683,7 +683,6 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
>  void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
>  bool intel_ddi_pll_select(struct intel_crtc *crtc);
> -void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
>  void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
>  void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
> @@ -746,7 +745,6 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -void intel_disable_shared_dpll(struct intel_crtc *crtc);
>  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
>  void intel_put_shared_dpll(struct intel_crtc *crtc);
>  
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 00/66] runtime pm for DPMS

[Kumar, Shobhit]

>>    drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
>>    drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
>>    drm/i915: Shovel hw setup code out of ilk_crtc_mode_set
>>    drm/i915: Shovel hw setup code out of hsw_crtc_mode_set
>>    drm/i915: Extract i9xx_set_pll_dividers
>>    drm/i915: Extract vlv_prepare_pll
>>
>> gmch pll moved out of crtc mode_set callbacks into ->enable hooks
>
> Reviewer: Shobhit Kumar

Looks good. For patch 30-35

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>

Regards
Shobhit

Re: [PATCH 23/66] drm/i915/dsi: Remove ->mode_set callback

[Kumar, Shobhit]

On 4/25/2014 3:24 AM, Daniel Vetter wrote:
> Looking at our current dsi driver I note that:
> - We don't have any slave driver right now.
> - There's zero support for the hardware state readout and cross check
>    code.
> - All the modeset state seems to be tracked in the intel_dsi structure
>    instead of the pipe config.
>
> Given all that I can't properly audit the dsi ->mode_set callback. So
> just do it as the first thing in the ->pre_pll_enable hook and hope
> for the best.
>

Though this is merged, given the uncertainty around this in absence of 
panel driver.

Verified-by: Shobhit Kumar <shobhit.kumar@intel.com>

Regards
Shobhit

Re: [PATCH 23/66] drm/i915/dsi: Remove ->mode_set callback

[Daniel Vetter]

On Tue, May 20, 2014 at 05:29:46PM +0530, Kumar, Shobhit wrote:
> On 4/25/2014 3:24 AM, Daniel Vetter wrote:
> >Looking at our current dsi driver I note that:
> >- We don't have any slave driver right now.
> >- There's zero support for the hardware state readout and cross check
> >   code.
> >- All the modeset state seems to be tracked in the intel_dsi structure
> >   instead of the pipe config.
> >
> >Given all that I can't properly audit the dsi ->mode_set callback. So
> >just do it as the first thing in the ->pre_pll_enable hook and hope
> >for the best.
> >
> 
> Though this is merged, given the uncertainty around this in absence of panel
> driver.
> 
> Verified-by: Shobhit Kumar <shobhit.kumar@intel.com>

Yeah we have a bit an ugly situation with dsi :( Thanks for checking.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 38/66] drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

[Daniel Vetter]

On Tue, May 20, 2014 at 11:29:54AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:14PM +0200, Daniel Vetter wrote:
> > Besides the fairly useless BUG_ON the logic is completely generic
> > and cane be used on any platform what wants to reuse the shared
> > dpll support code.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Queued up to this patch, thanks everyone for the review.
-Daniel

> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 8 +++-----
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 96bab640399f..1513d9fceebe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1568,21 +1568,19 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> >  }
> >  
> >  /**
> > - * ironlake_enable_shared_dpll - enable PCH PLL
> > + * intel_enable_shared_dpll - enable PCH PLL
> >   * @dev_priv: i915 private structure
> >   * @pipe: pipe PLL to enable
> >   *
> >   * The PCH PLL needs to be enabled before the PCH transcoder, since it
> >   * drives the transcoder clock.
> >   */
> > -static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
> > +static void intel_enable_shared_dpll(struct intel_crtc *crtc)
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> >  
> > -	/* PCH PLLs only available on ILK, SNB and IVB */
> > -	BUG_ON(INTEL_INFO(dev)->gen < 5);
> >  	if (WARN_ON(pll == NULL))
> >  		return;
> >  
> > @@ -3328,7 +3326,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> >  	 * Note that enable_shared_dpll tries to do the right thing, but
> >  	 * get_shared_dpll unconditionally resets the pll - we need that to have
> >  	 * the right LVDS enable sequence. */
> > -	ironlake_enable_shared_dpll(intel_crtc);
> > +	intel_enable_shared_dpll(intel_crtc);
> >  
> >  	/* set transcoder timing, panel must allow it */
> >  	assert_panel_unlocked(dev_priv, pipe);
> > -- 
> > 1.8.1.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> All the other checks also check hw state, so checking our software
> refcounts for the plls looks a bit odd.

As I mentioned before, this contradicts your own previous review of
the patch that added this code. In addition, you said many times that
we should do SW checks instead of HW checks when possible.

What should be looking odd here is that we check registers directly
for the other stuff, instead of looking at some struct :)

> Also this will simplify the
> conversion over to the shared dpll framework, which itself has massive
> amounts of checks to make sure that we never leave a display pll
> enabled when we shouldn't.

What you wrote above is a nice reason to check the new shared DPLL
structs instead of the registers directly: it has tons of WARNs, so
it's unlikely the structs will be wrong.

>
> So after that conversion we should stil have a good enough coverage of
> asserts for entering pc8/runtime pm on hsw/bdw.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1513d9fceebe..22b3d74f9ecc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6926,7 +6926,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
>  {
>         struct drm_device *dev = dev_priv->dev;
> -       struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
>         struct intel_crtc *crtc;
>
>         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
> @@ -6934,9 +6933,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
>                      pipe_name(crtc->pipe));
>
>         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
> -       WARN(plls->spll_refcount, "SPLL enabled\n");
> -       WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
> -       WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
> +       WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> +       WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> +       WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
>         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
>         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
>              "CPU PWM1 enabled\n");
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 41/66] drm/i915: Clean up WRPLL/SPLL #defines

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Luckily the bit definitions match, but it's still confusing
> to use one when handling the other. So sprinkle some OCD over
> the #defines to make them match and use the right version in
> each place.
>
> Maybe we should unify these definitions completely, but that
> can always be done sometime in the future.

I agree that using SPLL definitions on WRPLL code was very confusing.
But I think I still prefer the longer field names, since they are more
meaningful. If "select" is too big, we could at least use "sel".

With or without that: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  7 ++++---
>  drivers/gpu/drm/i915/intel_ddi.c | 12 ++++++------
>  2 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8f845556503e..64d40f22e708 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5505,9 +5505,10 @@ enum punit_power_well {
>  #define WRPLL_CTL1                     0x46040
>  #define WRPLL_CTL2                     0x46060
>  #define  WRPLL_PLL_ENABLE              (1<<31)
> -#define  WRPLL_PLL_SELECT_SSC          (0x01<<28)
> -#define  WRPLL_PLL_SELECT_NON_SSC      (0x02<<28)
> -#define  WRPLL_PLL_SELECT_LCPLL_2700   (0x03<<28)
> +#define  WRPLL_PLL_SSC                 (1<<28)
> +#define  WRPLL_PLL_NON_SSC             (2<<28)
> +#define  WRPLL_PLL_LCPLL               (3<<28)
> +#define  WRPLL_PLL_REF_MASK            (3<<28)
>  /* WRPLL divider programming */
>  #define  WRPLL_DIVIDER_REFERENCE(x)    ((x)<<0)
>  #define  WRPLL_DIVIDER_REF_MASK                (0xff)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 16ec6aee3df7..09ae104d9c2b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -588,9 +588,9 @@ static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
>         u32 wrpll;
>
>         wrpll = I915_READ(reg);
> -       switch (wrpll & SPLL_PLL_REF_MASK) {
> -       case SPLL_PLL_SSC:
> -       case SPLL_PLL_NON_SSC:
> +       switch (wrpll & WRPLL_PLL_REF_MASK) {
> +       case WRPLL_PLL_SSC:
> +       case WRPLL_PLL_NON_SSC:
>                 /*
>                  * We could calculate spread here, but our checking
>                  * code only cares about 5% accuracy, and spread is a max of
> @@ -598,7 +598,7 @@ static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
>                  */
>                 refclk = 135;
>                 break;
> -       case SPLL_PLL_LCPLL:
> +       case WRPLL_PLL_LCPLL:
>                 refclk = LC_FREQ;
>                 break;
>         default:
> @@ -780,7 +780,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>
>                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
>
> -               val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
> +               val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
>                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>                       WRPLL_DIVIDER_POST(p);
>
> @@ -879,7 +879,7 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
>
>                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
>
> -               new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
> +               new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
>                           WRPLL_DIVIDER_REFERENCE(r2) |
>                           WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
>
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 42/66] drm/i915: Make intel_wait_for_pipe_off static

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Noticed while reading around.

That's because you killed the intel_tv.c caller in patch 06/66.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_drv.h     | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 22b3d74f9ecc..713563faeafd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -854,7 +854,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
>   *   ends up stopping at the start of the next frame).
>   *
>   */
> -void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
> +static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
>         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c85f5e5ddc7c..2be0b104fbec 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -719,7 +719,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
>  enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
>                                              enum pipe pipe);
>  void intel_wait_for_vblank(struct drm_device *dev, int pipe);
> -void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
>  int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
>  void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>                          struct intel_digital_port *dport);
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 40/66] drm/i915: Remove spll_refcount for hsw

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> SPLL would be a reference clock we could potentially share,
> especially if we want to use the SSC mode. But currently we
> don't, so let's rip out this complexity for a simpler conversion
> to the new display pll framework.

I'm really not a fan of this patch, I think it goes in the opposite
way of where we want to be. We already talked a few times about adding
sharing support, and I even recently considered adding a
"i915.edp_use_ssc" module option and ask some bug reporters to test
them. Also, adding the SPLL support will be another way to prove that
your "shared DPLL" code is flexible enough to handle the all the
possibilities generated by the creative minds of the HW developers.
Can you please include SPLL in your conversion?

Thanks,
Paulo


>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 -
>  drivers/gpu/drm/i915/intel_ddi.c | 41 +++++++++++++---------------------------
>  2 files changed, 13 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e6c16068010f..b6eac92e0a22 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -221,7 +221,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
>                             struct intel_link_m_n *m_n);
>
>  struct intel_ddi_plls {
> -       int spll_refcount;
>         int wrpll1_refcount;
>         int wrpll2_refcount;
>  };
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 271ce19ee880..16ec6aee3df7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -394,14 +394,11 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>
>         switch (intel_crtc->ddi_pll_sel) {
>         case PORT_CLK_SEL_SPLL:
> -               plls->spll_refcount--;
> -               if (plls->spll_refcount == 0) {
> -                       DRM_DEBUG_KMS("Disabling SPLL\n");
> -                       val = I915_READ(SPLL_CTL);
> -                       WARN_ON(!(val & SPLL_PLL_ENABLE));
> -                       I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
> -                       POSTING_READ(SPLL_CTL);
> -               }
> +               DRM_DEBUG_KMS("Disabling SPLL\n");
> +               val = I915_READ(SPLL_CTL);
> +               WARN_ON(!(val & SPLL_PLL_ENABLE));
> +               I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
> +               POSTING_READ(SPLL_CTL);
>                 break;
>         case PORT_CLK_SEL_WRPLL1:
>                 plls->wrpll1_refcount--;
> @@ -425,7 +422,6 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>                 break;
>         }
>
> -       WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
>         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
>         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
>
> @@ -821,16 +817,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>                 }
>
>         } else if (type == INTEL_OUTPUT_ANALOG) {
> -               if (plls->spll_refcount == 0) {
> -                       DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
> -                                     pipe_name(pipe));
> -                       plls->spll_refcount++;
> -                       intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
> -               } else {
> -                       DRM_ERROR("SPLL already in use\n");
> -                       return false;
> -               }
> -
> +               DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
> +                             pipe_name(pipe));
> +               intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
>         } else {
>                 WARN(1, "Invalid DDI encoder type %d\n", type);
>                 return false;
> @@ -869,13 +858,13 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
>                 return;
>
>         case PORT_CLK_SEL_SPLL:
> -               pll_name = "SPLL";
> -               reg = SPLL_CTL;
> -               refcount = plls->spll_refcount;
>                 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
>                           SPLL_PLL_SSC;
> -               break;
> -
> +               WARN(I915_READ(SPLL_CTL) & enable_bit, "SPLL already enabled\n");
> +               I915_WRITE(SPLL_CTL, new_val);
> +               POSTING_READ(SPLL_CTL);
> +               udelay(20);
> +               return;
>         case PORT_CLK_SEL_WRPLL1:
>         case PORT_CLK_SEL_WRPLL2:
>                 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
> @@ -1186,7 +1175,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>         enum pipe pipe;
>         struct intel_crtc *intel_crtc;
>
> -       dev_priv->ddi_plls.spll_refcount = 0;
>         dev_priv->ddi_plls.wrpll1_refcount = 0;
>         dev_priv->ddi_plls.wrpll2_refcount = 0;
>
> @@ -1203,9 +1191,6 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>                                                                  pipe);
>
>                 switch (intel_crtc->ddi_pll_sel) {
> -               case PORT_CLK_SEL_SPLL:
> -                       dev_priv->ddi_plls.spll_refcount++;
> -                       break;
>                 case PORT_CLK_SEL_WRPLL1:
>                         dev_priv->ddi_plls.wrpll1_refcount++;
>                         break;
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 43/66] drm/i915: Disable pipe before ports on ilk

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> The modeset sequence docs are very clear that we should disable the
> pipe before we switch off any ports, for both pch ports and the cpu
> edp port.
>
> In practice it doesn't seem to matter too much since for non-DP pch
> ports it only matters that the pch transcoder is still on. And for cpu
> edp ports it either doesn't seem to matter or we're quick enough.
>
> But for DP pch ports we have a regular stream of bug reports where the
> cpu pipe seems to be stuck and won't turn off. This change should
> address this.
>
> This should also help with using a nuclear pageflip atomically switch
> off all planes, since it moves that ahead of any other disabling
> action.
>
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=62251
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52061
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54687
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67462
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

This patch doesn't make us spec-compliant either.

For example, the spec says we need to disable audio, backlight and the
panel power *before* we disable the pipe. This is done by
intel_disable_dp on IVB, which is, today, at the correct order. After
this patch, we will be doing all this *after* we disable the pipe,
which is not what the spec says we should do.

Also, we have ->disable and ->post_disable for a reason, and it kinda
looks like you're making ILK's ->disable do what ->post_disable should
be doing. It seems what we should do if we want to be correct is to
mode stuff from ->disable to ->post_disable.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 713563faeafd..82ad84eefc8d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3924,14 +3924,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>
>         ilk_crtc_disable_planes(crtc);
>
> -       for_each_encoder_on_crtc(dev, crtc, encoder)
> -               encoder->disable(encoder);
> -
>         if (intel_crtc->config.has_pch_encoder)
>                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
>
>         intel_disable_pipe(dev_priv, pipe);
>
> +       for_each_encoder_on_crtc(dev, crtc, encoder)
> +               encoder->disable(encoder);
> +
>         ironlake_pfit_disable(intel_crtc);
>
>         for_each_encoder_on_crtc(dev, crtc, encoder)
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

[Daniel Vetter]

On Thu, May 22, 2014 at 03:10:37PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > All the other checks also check hw state, so checking our software
> > refcounts for the plls looks a bit odd.
> 
> As I mentioned before, this contradicts your own previous review of
> the patch that added this code. In addition, you said many times that
> we should do SW checks instead of HW checks when possible.
> 
> What should be looking odd here is that we check registers directly
> for the other stuff, instead of looking at some struct :)
> 
> > Also this will simplify the
> > conversion over to the shared dpll framework, which itself has massive
> > amounts of checks to make sure that we never leave a display pll
> > enabled when we shouldn't.
> 
> What you wrote above is a nice reason to check the new shared DPLL
> structs instead of the registers directly: it has tons of WARNs, so
> it's unlikely the structs will be wrong.

If I've done this correctly this should happen a few patches later on. If
not I can throw a new patch on top. I'll check this.
-Daniel
> 
> >
> > So after that conversion we should stil have a good enough coverage of
> > asserts for entering pc8/runtime pm on hsw/bdw.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 7 +++----
> >  1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 1513d9fceebe..22b3d74f9ecc 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6926,7 +6926,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> >  {
> >         struct drm_device *dev = dev_priv->dev;
> > -       struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
> >         struct intel_crtc *crtc;
> >
> >         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
> > @@ -6934,9 +6933,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> >                      pipe_name(crtc->pipe));
> >
> >         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
> > -       WARN(plls->spll_refcount, "SPLL enabled\n");
> > -       WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
> > -       WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
> > +       WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> > +       WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> > +       WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> >         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
> >         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> >              "CPU PWM1 enabled\n");
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 44/66] drm/i915: Pass port explicitly to intel_ddi_get_hw_state

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Well, the newly created intel_ddi_get_port_state.
>
> In general intel_ddi.c has way too intimate knowledge with everyone
> else as exemplified with all the encoder/connector noodling and the
> massive exported function list.
>
> As a first step explictly pass around the port, first in the encoder
> callback.

I don't really see the benefit of this patch, and the sentences above
don't really help me. Can you please clarify?

Anyway, the patch is correct, so: Reviewed-by: Paulo Zanoni
<paulo.r.zanoni@intel.com>

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_crt.c |  8 +++++++-
>  drivers/gpu/drm/i915/intel_ddi.c | 13 ++++++++++---
>  drivers/gpu/drm/i915/intel_drv.h |  3 ++-
>  3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 22d8347f7838..f34d1df88918 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -137,6 +137,12 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
>         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
>  }
>
> +static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
> +                                enum pipe *pipe)
> +{
> +       return intel_ddi_get_port_state(encoder, pipe, PORT_E);
> +}
> +
>  /* Note: The caller is required to filter out dpms modes not supported by the
>   * platform. */
>  static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> @@ -858,7 +864,7 @@ void intel_crt_init(struct drm_device *dev)
>                 crt->base.hpd_pin = HPD_CRT;
>         if (HAS_DDI(dev)) {
>                 crt->base.get_config = hsw_crt_get_config;
> -               crt->base.get_hw_state = intel_ddi_get_hw_state;
> +               crt->base.get_hw_state = hsw_crt_get_hw_state;
>         } else {
>                 crt->base.get_config = intel_crt_get_config;
>                 crt->base.get_hw_state = intel_crt_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 09ae104d9c2b..ace43c6a6fa4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1082,12 +1082,11 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
>         }
>  }
>
> -bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> -                           enum pipe *pipe)
> +bool intel_ddi_get_port_state(struct intel_encoder *encoder,
> +                             enum pipe *pipe, enum port port)
>  {
>         struct drm_device *dev = encoder->base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> -       enum port port = intel_ddi_get_encoder_port(encoder);
>         enum intel_display_power_domain power_domain;
>         u32 tmp;
>         int i;
> @@ -1135,6 +1134,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>         return false;
>  }
>
> +static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> +                                  enum pipe *pipe)
> +{
> +       enum port port = intel_ddi_get_encoder_port(encoder);
> +
> +       return intel_ddi_get_port_state(encoder, pipe, port);
> +}
> +
>  static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
>                                        enum pipe pipe)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 2be0b104fbec..ba727b11014a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -671,7 +671,8 @@ void intel_prepare_ddi(struct drm_device *dev);
>  void hsw_fdi_link_train(struct drm_crtc *crtc);
>  void intel_ddi_init(struct drm_device *dev, enum port port);
>  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
> -bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
> +bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
> +                             enum port port);
>  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
>  void intel_ddi_pll_init(struct drm_device *dev);
>  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 40/66] drm/i915: Remove spll_refcount for hsw

[Daniel Vetter]

On Thu, May 22, 2014 at 03:41:25PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > SPLL would be a reference clock we could potentially share,
> > especially if we want to use the SSC mode. But currently we
> > don't, so let's rip out this complexity for a simpler conversion
> > to the new display pll framework.
> 
> I'm really not a fan of this patch, I think it goes in the opposite
> way of where we want to be. We already talked a few times about adding
> sharing support, and I even recently considered adding a
> "i915.edp_use_ssc" module option and ask some bug reporters to test
> them. Also, adding the SPLL support will be another way to prove that
> your "shared DPLL" code is flexible enough to handle the all the
> possibilities generated by the creative minds of the HW developers.
> Can you please include SPLL in your conversion?

Until we actually know that we need it I don't see a reason to do it. And
for a quick debug patch you can always just disable vga on bdw and simply
use the spll for edp without any sharing logic.

But if you wonder who we should integrate SPLL sharing into this framework
it's straightforward:
- Add a possible_dpll_mask to the pipe_config, and pre-fill it in the
  encoder->compute_config masks.
- Add spll state the the dpll_hw_state structure, pre-fill that in the
  encoder->compute_config hooks (might as well do it right)
- add checks for the possible_dpll_mask in the get_shared_dpll function

Bonus point: We can ditch the ibx special case.

Or you go even simpler: If we need edp SSC _and_ possible VGA we only let
the SPLL run at 2.7GHz.

Then add a 2nd shared_spll to dev_priv which uses the shared dpll
functions and all that logic (might need to frob the interfaces a bit) but
outside of the selection logic (since we always have the same
configuration). Will be a bit more messy since we need to special-case
hw state readout code and a few other places.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 39/66] drm/i915: Check hw state in assert_can_disable_lcpll

[Daniel Vetter]

On Thu, May 22, 2014 at 9:26 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, May 22, 2014 at 03:10:37PM -0300, Paulo Zanoni wrote:
>> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
>> > All the other checks also check hw state, so checking our software
>> > refcounts for the plls looks a bit odd.
>>
>> As I mentioned before, this contradicts your own previous review of
>> the patch that added this code. In addition, you said many times that
>> we should do SW checks instead of HW checks when possible.
>>
>> What should be looking odd here is that we check registers directly
>> for the other stuff, instead of looking at some struct :)
>>
>> > Also this will simplify the
>> > conversion over to the shared dpll framework, which itself has massive
>> > amounts of checks to make sure that we never leave a display pll
>> > enabled when we shouldn't.
>>
>> What you wrote above is a nice reason to check the new shared DPLL
>> structs instead of the registers directly: it has tons of WARNs, so
>> it's unlikely the structs will be wrong.
>
> If I've done this correctly this should happen a few patches later on. If
> not I can throw a new patch on top. I'll check this.

Ah, actually we don't need it any more, the new stuff is much better ;-)

assert_can_disable_lcpll checks crtc->active for all pipes. And the
modeset state checker makes sure that the refcounts perfectly match
the crtcs, i.e. wrpll_refcount = \sum crtc->active. This is how we
check the sw side of things. Adding yet another sw check here feels
like too much overkill.y
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 45/66] drm/i915: Unexport intel_ddi_connector_get_hw_state

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> The connector->get_hw_state function is actually platform dependent.
> So move it out of the shared connector init functions. This allows us
> to drop another intel_ddi.c export.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

The nice thing about the current code is that intel_ddi_init(),
intel_hdmi_init() and intel_dp_init() only init encoder-specific data,
and the xx_connector_init() functions only init connector-specific
data. This patch will break this abstraction. I think the cost of
breaking the organization just to unexport a function is not worth it.

Also, see below:

> ---
>  drivers/gpu/drm/i915/intel_ddi.c  | 10 +++++++---
>  drivers/gpu/drm/i915/intel_dp.c   |  5 +----
>  drivers/gpu/drm/i915/intel_drv.h  |  1 -
>  drivers/gpu/drm/i915/intel_hdmi.c |  5 +----
>  4 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ace43c6a6fa4..afa1e87c54cc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1037,7 +1037,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>         I915_WRITE(reg, val);
>  }
>
> -bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
> +static bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
>  {
>         struct drm_device *dev = intel_connector->base.dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1689,13 +1689,17 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>         intel_encoder->cloneable = 0;
>         intel_encoder->hot_plug = intel_ddi_hot_plug;
>
> -       if (init_dp)
> +       if (init_dp) {
>                 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
> +               dp_connector->get_hw_state = intel_ddi_connector_get_hw_state;

This can segfault.


> +       }
>
>         /* In theory we don't need the encoder->type check, but leave it just in
>          * case we have some really bad VBTs... */
> -       if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
> +       if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
>                 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
> +               hdmi_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> +       }
>
>         if (!dp_connector && !hdmi_connector) {
>                 drm_encoder_cleanup(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5746fe22dde3..ca94be9554f4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3931,10 +3931,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>         intel_connector_attach_encoder(intel_connector, intel_encoder);
>         drm_sysfs_connector_add(connector);
>
> -       if (HAS_DDI(dev))
> -               intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> -       else
> -               intel_connector->get_hw_state = intel_connector_get_hw_state;
>         intel_connector->unregister = intel_dp_connector_unregister;
>
>         /* Set up the hotplug pin. */
> @@ -4043,4 +4039,5 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>                 kfree(intel_dig_port);
>                 kfree(intel_connector);
>         }
> +       intel_connector->get_hw_state = intel_connector_get_hw_state;

This can also segfault.


>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ba727b11014a..1c093e71db7d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -686,7 +686,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc);
>  void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
>  void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
> -bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
>  void intel_ddi_fdi_disable(struct drm_crtc *crtc);
>  void intel_ddi_get_config(struct intel_encoder *encoder,
>                           struct intel_crtc_config *pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index ced93bd33f80..b748bb39347c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1328,10 +1328,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>                 intel_hdmi->set_infoframes = cpt_set_infoframes;
>         }
>
> -       if (HAS_DDI(dev))
> -               intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> -       else
> -               intel_connector->get_hw_state = intel_connector_get_hw_state;
>         intel_connector->unregister = intel_connector_unregister;
>
>         intel_hdmi_add_properties(intel_hdmi, connector);
> @@ -1400,4 +1396,5 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>         intel_dig_port->dp.output_reg = 0;
>
>         intel_hdmi_init_connector(intel_dig_port, intel_connector);
> +       intel_connector->get_hw_state = intel_connector_get_hw_state;
>  }
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 43/66] drm/i915: Disable pipe before ports on ilk

[Daniel Vetter]

On Thu, May 22, 2014 at 04:25:05PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > The modeset sequence docs are very clear that we should disable the
> > pipe before we switch off any ports, for both pch ports and the cpu
> > edp port.
> >
> > In practice it doesn't seem to matter too much since for non-DP pch
> > ports it only matters that the pch transcoder is still on. And for cpu
> > edp ports it either doesn't seem to matter or we're quick enough.
> >
> > But for DP pch ports we have a regular stream of bug reports where the
> > cpu pipe seems to be stuck and won't turn off. This change should
> > address this.
> >
> > This should also help with using a nuclear pageflip atomically switch
> > off all planes, since it moves that ahead of any other disabling
> > action.
> >
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=62251
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52061
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54687
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67462
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> This patch doesn't make us spec-compliant either.
> 
> For example, the spec says we need to disable audio, backlight and the
> panel power *before* we disable the pipe. This is done by
> intel_disable_dp on IVB, which is, today, at the correct order. After
> this patch, we will be doing all this *after* we disable the pipe,
> which is not what the spec says we should do.
> 
> Also, we have ->disable and ->post_disable for a reason, and it kinda
> looks like you're making ILK's ->disable do what ->post_disable should
> be doing. It seems what we should do if we want to be correct is to
> mode stuff from ->disable to ->post_disable.

Oops, that patch here shouldn't be in this series. Somehow I've screwed up
my branch management, please ignore.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 713563faeafd..82ad84eefc8d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3924,14 +3924,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
> >
> >         ilk_crtc_disable_planes(crtc);
> >
> > -       for_each_encoder_on_crtc(dev, crtc, encoder)
> > -               encoder->disable(encoder);
> > -
> >         if (intel_crtc->config.has_pch_encoder)
> >                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
> >
> >         intel_disable_pipe(dev_priv, pipe);
> >
> > +       for_each_encoder_on_crtc(dev, crtc, encoder)
> > +               encoder->disable(encoder);
> > +
> >         ironlake_pfit_disable(intel_crtc);
> >
> >         for_each_encoder_on_crtc(dev, crtc, encoder)
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> The pch encoder case really isn't anything generic on hsw:
> - It's for the vga port only and
> - the vga port does only exist on some hsw platforms.
>
> Imo it helps the generic code flow a lot if we shovel all this into
> hsw specific enable/disable hooks. A bonus is that some of our largest
> files (intel_ddi.c and intel_display.c) will lose a pile of really big
> functions.
>
> Step one is to move the fdi link training code.

I don't think that helps much, since the other fdi link train code is
still at intel_display.c, and even if the only thing that needs fdi
link training on HSW is CRT, fdi link training is really _not_ a CRT
thing. So IMHO we're breaking an abstraction here by putting fdi link
training in CRT code. Also, the fact that HSW+ won't be using
dev_priv->display.fdi_link_train will makes things even more confusing
for people reading our code.

I'd really prefer if we merge
http://patchwork.freedesktop.org/patch/24019/ instead. Or something
based on that.


>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_crt.c     | 136 +++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_ddi.c     | 134 +---------------------------------
>  drivers/gpu/drm/i915/intel_display.c |   4 --
>  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
>  4 files changed, 140 insertions(+), 137 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index f34d1df88918..2d8f4fe1b450 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -143,6 +143,141 @@ static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
>         return intel_ddi_get_port_state(encoder, pipe, PORT_E);
>  }
>
> +static const long hsw_ddi_buf_ctl_values[] = {
> +       DDI_BUF_EMP_400MV_0DB_HSW,
> +       DDI_BUF_EMP_400MV_3_5DB_HSW,
> +       DDI_BUF_EMP_400MV_6DB_HSW,
> +       DDI_BUF_EMP_400MV_9_5DB_HSW,
> +       DDI_BUF_EMP_600MV_0DB_HSW,
> +       DDI_BUF_EMP_600MV_3_5DB_HSW,
> +       DDI_BUF_EMP_600MV_6DB_HSW,
> +       DDI_BUF_EMP_800MV_0DB_HSW,
> +       DDI_BUF_EMP_800MV_3_5DB_HSW
> +};
> +
> +static void hsw_fdi_link_train(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +       u32 temp, i, rx_ctl_val;
> +
> +       /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> +        * mode set "sequence for CRT port" document:
> +        * - TP1 to TP2 time with the default value
> +        * - FDI delay to 90h
> +        *
> +        * WaFDIAutoLinkSetTimingOverrride:hsw
> +        */
> +       I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> +                                 FDI_RX_PWRDN_LANE0_VAL(2) |
> +                                 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> +
> +       /* Enable the PCH Receiver FDI PLL */
> +       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> +                    FDI_RX_PLL_ENABLE |
> +                    FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> +       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +       POSTING_READ(_FDI_RXA_CTL);
> +       udelay(220);
> +
> +       /* Switch from Rawclk to PCDclk */
> +       rx_ctl_val |= FDI_PCDCLK;
> +       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +
> +       /* Configure Port Clock Select */
> +       I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> +
> +       /* Start the training iterating through available voltages and emphasis,
> +        * testing each value twice. */
> +       for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> +               /* Configure DP_TP_CTL with auto-training */
> +               I915_WRITE(DP_TP_CTL(PORT_E),
> +                                       DP_TP_CTL_FDI_AUTOTRAIN |
> +                                       DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> +                                       DP_TP_CTL_LINK_TRAIN_PAT1 |
> +                                       DP_TP_CTL_ENABLE);
> +
> +               /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
> +                * DDI E does not support port reversal, the functionality is
> +                * achieved on the PCH side in FDI_RX_CTL, so no need to set the
> +                * port reversal bit */
> +               I915_WRITE(DDI_BUF_CTL(PORT_E),
> +                          DDI_BUF_CTL_ENABLE |
> +                          ((intel_crtc->config.fdi_lanes - 1) << 1) |
> +                          hsw_ddi_buf_ctl_values[i / 2]);
> +               POSTING_READ(DDI_BUF_CTL(PORT_E));
> +
> +               udelay(600);
> +
> +               /* Program PCH FDI Receiver TU */
> +               I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
> +
> +               /* Enable PCH FDI Receiver with auto-training */
> +               rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> +               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +               POSTING_READ(_FDI_RXA_CTL);
> +
> +               /* Wait for FDI receiver lane calibration */
> +               udelay(30);
> +
> +               /* Unset FDI_RX_MISC pwrdn lanes */
> +               temp = I915_READ(_FDI_RXA_MISC);
> +               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> +               I915_WRITE(_FDI_RXA_MISC, temp);
> +               POSTING_READ(_FDI_RXA_MISC);
> +
> +               /* Wait for FDI auto training time */
> +               udelay(5);
> +
> +               temp = I915_READ(DP_TP_STATUS(PORT_E));
> +               if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
> +                       DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
> +
> +                       /* Enable normal pixel sending for FDI */
> +                       I915_WRITE(DP_TP_CTL(PORT_E),
> +                                  DP_TP_CTL_FDI_AUTOTRAIN |
> +                                  DP_TP_CTL_LINK_TRAIN_NORMAL |
> +                                  DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> +                                  DP_TP_CTL_ENABLE);
> +
> +                       return;
> +               }
> +
> +               temp = I915_READ(DDI_BUF_CTL(PORT_E));
> +               temp &= ~DDI_BUF_CTL_ENABLE;
> +               I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
> +               POSTING_READ(DDI_BUF_CTL(PORT_E));
> +
> +               /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> +               temp = I915_READ(DP_TP_CTL(PORT_E));
> +               temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> +               temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +               I915_WRITE(DP_TP_CTL(PORT_E), temp);
> +               POSTING_READ(DP_TP_CTL(PORT_E));
> +
> +               intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> +
> +               rx_ctl_val &= ~FDI_RX_ENABLE;
> +               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> +               POSTING_READ(_FDI_RXA_CTL);
> +
> +               /* Reset FDI_RX_MISC pwrdn lanes */
> +               temp = I915_READ(_FDI_RXA_MISC);
> +               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> +               temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> +               I915_WRITE(_FDI_RXA_MISC, temp);
> +               POSTING_READ(_FDI_RXA_MISC);
> +       }
> +
> +       DRM_ERROR("FDI link training failed!\n");
> +}
> +
> +static void hsw_crt_pre_enable(struct intel_encoder *encoder)
> +{
> +       hsw_fdi_link_train(encoder->base.crtc);
> +}
> +
>  /* Note: The caller is required to filter out dpms modes not supported by the
>   * platform. */
>  static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> @@ -865,6 +1000,7 @@ void intel_crt_init(struct drm_device *dev)
>         if (HAS_DDI(dev)) {
>                 crt->base.get_config = hsw_crt_get_config;
>                 crt->base.get_hw_state = hsw_crt_get_hw_state;
> +               crt->base.pre_enable = hsw_crt_pre_enable;
>         } else {
>                 crt->base.get_config = intel_crt_get_config;
>                 crt->base.get_hw_state = intel_crt_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index afa1e87c54cc..13abde3e848f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -211,20 +211,8 @@ void intel_prepare_ddi(struct drm_device *dev)
>                 intel_prepare_ddi_buffers(dev, port);
>  }
>
> -static const long hsw_ddi_buf_ctl_values[] = {
> -       DDI_BUF_EMP_400MV_0DB_HSW,
> -       DDI_BUF_EMP_400MV_3_5DB_HSW,
> -       DDI_BUF_EMP_400MV_6DB_HSW,
> -       DDI_BUF_EMP_400MV_9_5DB_HSW,
> -       DDI_BUF_EMP_600MV_0DB_HSW,
> -       DDI_BUF_EMP_600MV_3_5DB_HSW,
> -       DDI_BUF_EMP_600MV_6DB_HSW,
> -       DDI_BUF_EMP_800MV_0DB_HSW,
> -       DDI_BUF_EMP_800MV_3_5DB_HSW
> -};
> -
> -static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> -                                   enum port port)
> +void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> +                            enum port port)
>  {
>         uint32_t reg = DDI_BUF_CTL(port);
>         int i;
> @@ -246,124 +234,6 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>   * DDI A (which is used for eDP)
>   */
>
> -void hsw_fdi_link_train(struct drm_crtc *crtc)
> -{
> -       struct drm_device *dev = crtc->dev;
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -       u32 temp, i, rx_ctl_val;
> -
> -       /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> -        * mode set "sequence for CRT port" document:
> -        * - TP1 to TP2 time with the default value
> -        * - FDI delay to 90h
> -        *
> -        * WaFDIAutoLinkSetTimingOverrride:hsw
> -        */
> -       I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> -                                 FDI_RX_PWRDN_LANE0_VAL(2) |
> -                                 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> -
> -       /* Enable the PCH Receiver FDI PLL */
> -       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> -                    FDI_RX_PLL_ENABLE |
> -                    FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> -       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -       POSTING_READ(_FDI_RXA_CTL);
> -       udelay(220);
> -
> -       /* Switch from Rawclk to PCDclk */
> -       rx_ctl_val |= FDI_PCDCLK;
> -       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -
> -       /* Configure Port Clock Select */
> -       I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> -
> -       /* Start the training iterating through available voltages and emphasis,
> -        * testing each value twice. */
> -       for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> -               /* Configure DP_TP_CTL with auto-training */
> -               I915_WRITE(DP_TP_CTL(PORT_E),
> -                                       DP_TP_CTL_FDI_AUTOTRAIN |
> -                                       DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> -                                       DP_TP_CTL_LINK_TRAIN_PAT1 |
> -                                       DP_TP_CTL_ENABLE);
> -
> -               /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
> -                * DDI E does not support port reversal, the functionality is
> -                * achieved on the PCH side in FDI_RX_CTL, so no need to set the
> -                * port reversal bit */
> -               I915_WRITE(DDI_BUF_CTL(PORT_E),
> -                          DDI_BUF_CTL_ENABLE |
> -                          ((intel_crtc->config.fdi_lanes - 1) << 1) |
> -                          hsw_ddi_buf_ctl_values[i / 2]);
> -               POSTING_READ(DDI_BUF_CTL(PORT_E));
> -
> -               udelay(600);
> -
> -               /* Program PCH FDI Receiver TU */
> -               I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
> -
> -               /* Enable PCH FDI Receiver with auto-training */
> -               rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> -               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -               POSTING_READ(_FDI_RXA_CTL);
> -
> -               /* Wait for FDI receiver lane calibration */
> -               udelay(30);
> -
> -               /* Unset FDI_RX_MISC pwrdn lanes */
> -               temp = I915_READ(_FDI_RXA_MISC);
> -               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> -               I915_WRITE(_FDI_RXA_MISC, temp);
> -               POSTING_READ(_FDI_RXA_MISC);
> -
> -               /* Wait for FDI auto training time */
> -               udelay(5);
> -
> -               temp = I915_READ(DP_TP_STATUS(PORT_E));
> -               if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
> -                       DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
> -
> -                       /* Enable normal pixel sending for FDI */
> -                       I915_WRITE(DP_TP_CTL(PORT_E),
> -                                  DP_TP_CTL_FDI_AUTOTRAIN |
> -                                  DP_TP_CTL_LINK_TRAIN_NORMAL |
> -                                  DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> -                                  DP_TP_CTL_ENABLE);
> -
> -                       return;
> -               }
> -
> -               temp = I915_READ(DDI_BUF_CTL(PORT_E));
> -               temp &= ~DDI_BUF_CTL_ENABLE;
> -               I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
> -               POSTING_READ(DDI_BUF_CTL(PORT_E));
> -
> -               /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> -               temp = I915_READ(DP_TP_CTL(PORT_E));
> -               temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> -               temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -               I915_WRITE(DP_TP_CTL(PORT_E), temp);
> -               POSTING_READ(DP_TP_CTL(PORT_E));
> -
> -               intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> -
> -               rx_ctl_val &= ~FDI_RX_ENABLE;
> -               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> -               POSTING_READ(_FDI_RXA_CTL);
> -
> -               /* Reset FDI_RX_MISC pwrdn lanes */
> -               temp = I915_READ(_FDI_RXA_MISC);
> -               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> -               temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> -               I915_WRITE(_FDI_RXA_MISC, temp);
> -               POSTING_READ(_FDI_RXA_MISC);
> -       }
> -
> -       DRM_ERROR("FDI link training failed!\n");
> -}
> -
>  static struct intel_encoder *
>  intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 82ad84eefc8d..80b34ac31d0a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3858,9 +3858,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>         if (intel_crtc->config.has_pch_encoder)
>                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
>
> -       if (intel_crtc->config.has_pch_encoder)
> -               dev_priv->display.fdi_link_train(crtc);
> -
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->pre_enable)
>                         encoder->pre_enable(encoder);
> @@ -11120,7 +11117,6 @@ static void intel_init_display(struct drm_device *dev)
>                         dev_priv->display.modeset_global_resources =
>                                 ivb_modeset_global_resources;
>                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> -                       dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>                         dev_priv->display.write_eld = haswell_write_eld;
>                         dev_priv->display.modeset_global_resources =
>                                 haswell_modeset_global_resources;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1c093e71db7d..7f1d7f675953 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -668,11 +668,12 @@ void intel_crt_init(struct drm_device *dev);
>
>  /* intel_ddi.c */
>  void intel_prepare_ddi(struct drm_device *dev);
> -void hsw_fdi_link_train(struct drm_crtc *crtc);
>  void intel_ddi_init(struct drm_device *dev, enum port port);
>  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
>  bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
>                               enum port port);
> +void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> +                            enum port port);
>  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
>  void intel_ddi_pll_init(struct drm_device *dev);
>  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 44/66] drm/i915: Pass port explicitly to intel_ddi_get_hw_state

[Daniel Vetter]

On Thu, May 22, 2014 at 04:38:07PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > Well, the newly created intel_ddi_get_port_state.
> >
> > In general intel_ddi.c has way too intimate knowledge with everyone
> > else as exemplified with all the encoder/connector noodling and the
> > massive exported function list.
> >
> > As a first step explictly pass around the port, first in the encoder
> > callback.
> 
> I don't really see the benefit of this patch, and the sentences above
> don't really help me. Can you please clarify?

intel_ddi.c gets called and calls functions all over the place, so this
tries to create a bit a better interface. Our modeset code is fairly
object-oriented overall and generally big scray switch statments which
decode from the object key indicate design problems.

So for that reasons there's a few patches in here to untangle things a bit
and raise clearer barriers between the different pieces.
-Daniel

> 
> Anyway, the patch is correct, so: Reviewed-by: Paulo Zanoni
> <paulo.r.zanoni@intel.com>
> 
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_crt.c |  8 +++++++-
> >  drivers/gpu/drm/i915/intel_ddi.c | 13 ++++++++++---
> >  drivers/gpu/drm/i915/intel_drv.h |  3 ++-
> >  3 files changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index 22d8347f7838..f34d1df88918 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -137,6 +137,12 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
> >         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
> >  }
> >
> > +static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
> > +                                enum pipe *pipe)
> > +{
> > +       return intel_ddi_get_port_state(encoder, pipe, PORT_E);
> > +}
> > +
> >  /* Note: The caller is required to filter out dpms modes not supported by the
> >   * platform. */
> >  static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> > @@ -858,7 +864,7 @@ void intel_crt_init(struct drm_device *dev)
> >                 crt->base.hpd_pin = HPD_CRT;
> >         if (HAS_DDI(dev)) {
> >                 crt->base.get_config = hsw_crt_get_config;
> > -               crt->base.get_hw_state = intel_ddi_get_hw_state;
> > +               crt->base.get_hw_state = hsw_crt_get_hw_state;
> >         } else {
> >                 crt->base.get_config = intel_crt_get_config;
> >                 crt->base.get_hw_state = intel_crt_get_hw_state;
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 09ae104d9c2b..ace43c6a6fa4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1082,12 +1082,11 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
> >         }
> >  }
> >
> > -bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> > -                           enum pipe *pipe)
> > +bool intel_ddi_get_port_state(struct intel_encoder *encoder,
> > +                             enum pipe *pipe, enum port port)
> >  {
> >         struct drm_device *dev = encoder->base.dev;
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > -       enum port port = intel_ddi_get_encoder_port(encoder);
> >         enum intel_display_power_domain power_domain;
> >         u32 tmp;
> >         int i;
> > @@ -1135,6 +1134,14 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> >         return false;
> >  }
> >
> > +static bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> > +                                  enum pipe *pipe)
> > +{
> > +       enum port port = intel_ddi_get_encoder_port(encoder);
> > +
> > +       return intel_ddi_get_port_state(encoder, pipe, port);
> > +}
> > +
> >  static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
> >                                        enum pipe pipe)
> >  {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 2be0b104fbec..ba727b11014a 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -671,7 +671,8 @@ void intel_prepare_ddi(struct drm_device *dev);
> >  void hsw_fdi_link_train(struct drm_crtc *crtc);
> >  void intel_ddi_init(struct drm_device *dev, enum port port);
> >  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
> > -bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
> > +bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
> > +                             enum port port);
> >  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
> >  void intel_ddi_pll_init(struct drm_device *dev);
> >  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 47/66] drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> With this all the pch pre-enable work has been moved into the special
> hsw crt encoder functions.

For the same reasons I gave in the other patches, I'm not convinced
this is an improvement to our code. It looks like we're just breaking
the abstraction exploiting the fact that CRT is the only FDI/PCH
output on Haswell. Now the HSW code will be significantly different
from the ILK/SNB/HSW code, and I really think this can be confusing to
people reading the code. I really think we shouldn't hide things
aren't specific to CRT inside CRT code.

Since on this series we're basically disagreeing on our opinions on
which coding style is the better, I think we should ask the other
developers to give their opinion too :)

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_crt.c     | 4 ++++
>  drivers/gpu/drm/i915/intel_display.c | 2 --
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 2d8f4fe1b450..d3cae57d942a 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -275,6 +275,10 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
>
>  static void hsw_crt_pre_enable(struct intel_encoder *encoder)
>  {
> +       struct drm_device *dev = encoder->base.dev;
> +
> +       intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
> +
>         hsw_fdi_link_train(encoder->base.crtc);
>  }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 80b34ac31d0a..43a40594841f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3855,8 +3855,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>         intel_crtc->active = true;
>
>         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
> -       if (intel_crtc->config.has_pch_encoder)
> -               intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
>
>         for_each_encoder_on_crtc(dev, crtc, encoder)
>                 if (encoder->pre_enable)
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

[PATCH] drm/i915: Unexport intel_ddi_connector_get_hw_state

[Daniel Vetter]

The connector->get_hw_state function is actually platform dependent.
So move it out of the shared connector init functions. This allows us
to drop another intel_ddi.c export.

v2: Fix segfaults when the dp connector fails to initialize (e.g. due
there not being a panel). Spotted by Paulo.

Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c  | 8 ++++++--
 drivers/gpu/drm/i915/intel_dp.c   | 6 ++----
 drivers/gpu/drm/i915/intel_drv.h  | 1 -
 drivers/gpu/drm/i915/intel_hdmi.c | 5 +----
 4 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ace43c6a6fa4..9e5c189c8100 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1037,7 +1037,7 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 	I915_WRITE(reg, val);
 }
 
-bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
+static bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 {
 	struct drm_device *dev = intel_connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1691,11 +1691,15 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 
 	if (init_dp)
 		dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
+	if (dp_connector)
+		dp_connector->get_hw_state = intel_ddi_connector_get_hw_state;
 
 	/* In theory we don't need the encoder->type check, but leave it just in
 	 * case we have some really bad VBTs... */
-	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
+	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
 		hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
+		hdmi_connector->get_hw_state = intel_ddi_connector_get_hw_state;
+	}
 
 	if (!dp_connector && !hdmi_connector) {
 		drm_encoder_cleanup(encoder);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5746fe22dde3..803d0b8f30f2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3931,10 +3931,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_connector_attach_encoder(intel_connector, intel_encoder);
 	drm_sysfs_connector_add(connector);
 
-	if (HAS_DDI(dev))
-		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
-	else
-		intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_dp_connector_unregister;
 
 	/* Set up the hotplug pin. */
@@ -4038,6 +4034,8 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 	intel_encoder->cloneable = 0;
 	intel_encoder->hot_plug = intel_dp_hot_plug;
 
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
+
 	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
 		drm_encoder_cleanup(encoder);
 		kfree(intel_dig_port);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ba727b11014a..1c093e71db7d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -686,7 +686,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc);
 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 void intel_ddi_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_config *pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ced93bd33f80..b748bb39347c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1328,10 +1328,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_hdmi->set_infoframes = cpt_set_infoframes;
 	}
 
-	if (HAS_DDI(dev))
-		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
-	else
-		intel_connector->get_hw_state = intel_connector_get_hw_state;
 	intel_connector->unregister = intel_connector_unregister;
 
 	intel_hdmi_add_properties(intel_hdmi, connector);
@@ -1400,4 +1396,5 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 	intel_dig_port->dp.output_reg = 0;
 
 	intel_hdmi_init_connector(intel_dig_port, intel_connector);
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
 }
-- 
1.8.1.4

Re: [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

[Daniel Vetter]

On Thu, May 22, 2014 at 05:28:05PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > The pch encoder case really isn't anything generic on hsw:
> > - It's for the vga port only and
> > - the vga port does only exist on some hsw platforms.
> >
> > Imo it helps the generic code flow a lot if we shovel all this into
> > hsw specific enable/disable hooks. A bonus is that some of our largest
> > files (intel_ddi.c and intel_display.c) will lose a pile of really big
> > functions.
> >
> > Step one is to move the fdi link training code.
> 
> I don't think that helps much, since the other fdi link train code is
> still at intel_display.c, and even if the only thing that needs fdi
> link training on HSW is CRT, fdi link training is really _not_ a CRT
> thing. So IMHO we're breaking an abstraction here by putting fdi link
> training in CRT code. Also, the fact that HSW+ won't be using
> dev_priv->display.fdi_link_train will makes things even more confusing
> for people reading our code.
> 
> I'd really prefer if we merge
> http://patchwork.freedesktop.org/patch/24019/ instead. Or something
> based on that.

Well my idea with all this was that even on hsw vga on the pch is a bit
the special case, and on bdw+ it's completely gone. So taking this out of
the common modeset code should help bdw+ a bit since now the modeset
sequence and our code really nicely align.

Also with ilk-ivb having the fdi code in the crtc functions made a lot of
sense since the big crossbar was in the pch. So doing everything up to the
pch crossbar, including all the fdi handling in crtc code, and everything
after that in encoder callbacks.

But on hsw+ we have the big crossbar on the cpu side, between the
transcoders and the ddi ports. So from a functional pov it makes much more
sense imo to have all the pipe/transcoder code in the crtc, and all the
ddi handling code in encoder callbacks. The pch and fdi link that hang off
ddi port E work more like a drm_bridge (but we don't need that since the
lpt pch will never be used outside of intel platforms).

So with this example, grouping all the fdi code together only groups
functions by their name. But moving the hsw fdi stuff into the crt encoder
groups the code by the behaviour of the hardware. And that's massively
different betweent ivb and hsw.

I hope this explains a bit my thinking here.
-Daniel
> 
> 
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_crt.c     | 136 +++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_ddi.c     | 134 +---------------------------------
> >  drivers/gpu/drm/i915/intel_display.c |   4 --
> >  drivers/gpu/drm/i915/intel_drv.h     |   3 +-
> >  4 files changed, 140 insertions(+), 137 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index f34d1df88918..2d8f4fe1b450 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -143,6 +143,141 @@ static bool hsw_crt_get_hw_state(struct intel_encoder *encoder,
> >         return intel_ddi_get_port_state(encoder, pipe, PORT_E);
> >  }
> >
> > +static const long hsw_ddi_buf_ctl_values[] = {
> > +       DDI_BUF_EMP_400MV_0DB_HSW,
> > +       DDI_BUF_EMP_400MV_3_5DB_HSW,
> > +       DDI_BUF_EMP_400MV_6DB_HSW,
> > +       DDI_BUF_EMP_400MV_9_5DB_HSW,
> > +       DDI_BUF_EMP_600MV_0DB_HSW,
> > +       DDI_BUF_EMP_600MV_3_5DB_HSW,
> > +       DDI_BUF_EMP_600MV_6DB_HSW,
> > +       DDI_BUF_EMP_800MV_0DB_HSW,
> > +       DDI_BUF_EMP_800MV_3_5DB_HSW
> > +};
> > +
> > +static void hsw_fdi_link_train(struct drm_crtc *crtc)
> > +{
> > +       struct drm_device *dev = crtc->dev;
> > +       struct drm_i915_private *dev_priv = dev->dev_private;
> > +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +       u32 temp, i, rx_ctl_val;
> > +
> > +       /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> > +        * mode set "sequence for CRT port" document:
> > +        * - TP1 to TP2 time with the default value
> > +        * - FDI delay to 90h
> > +        *
> > +        * WaFDIAutoLinkSetTimingOverrride:hsw
> > +        */
> > +       I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> > +                                 FDI_RX_PWRDN_LANE0_VAL(2) |
> > +                                 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> > +
> > +       /* Enable the PCH Receiver FDI PLL */
> > +       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> > +                    FDI_RX_PLL_ENABLE |
> > +                    FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> > +       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > +       POSTING_READ(_FDI_RXA_CTL);
> > +       udelay(220);
> > +
> > +       /* Switch from Rawclk to PCDclk */
> > +       rx_ctl_val |= FDI_PCDCLK;
> > +       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > +
> > +       /* Configure Port Clock Select */
> > +       I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> > +
> > +       /* Start the training iterating through available voltages and emphasis,
> > +        * testing each value twice. */
> > +       for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> > +               /* Configure DP_TP_CTL with auto-training */
> > +               I915_WRITE(DP_TP_CTL(PORT_E),
> > +                                       DP_TP_CTL_FDI_AUTOTRAIN |
> > +                                       DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> > +                                       DP_TP_CTL_LINK_TRAIN_PAT1 |
> > +                                       DP_TP_CTL_ENABLE);
> > +
> > +               /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
> > +                * DDI E does not support port reversal, the functionality is
> > +                * achieved on the PCH side in FDI_RX_CTL, so no need to set the
> > +                * port reversal bit */
> > +               I915_WRITE(DDI_BUF_CTL(PORT_E),
> > +                          DDI_BUF_CTL_ENABLE |
> > +                          ((intel_crtc->config.fdi_lanes - 1) << 1) |
> > +                          hsw_ddi_buf_ctl_values[i / 2]);
> > +               POSTING_READ(DDI_BUF_CTL(PORT_E));
> > +
> > +               udelay(600);
> > +
> > +               /* Program PCH FDI Receiver TU */
> > +               I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
> > +
> > +               /* Enable PCH FDI Receiver with auto-training */
> > +               rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> > +               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > +               POSTING_READ(_FDI_RXA_CTL);
> > +
> > +               /* Wait for FDI receiver lane calibration */
> > +               udelay(30);
> > +
> > +               /* Unset FDI_RX_MISC pwrdn lanes */
> > +               temp = I915_READ(_FDI_RXA_MISC);
> > +               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> > +               I915_WRITE(_FDI_RXA_MISC, temp);
> > +               POSTING_READ(_FDI_RXA_MISC);
> > +
> > +               /* Wait for FDI auto training time */
> > +               udelay(5);
> > +
> > +               temp = I915_READ(DP_TP_STATUS(PORT_E));
> > +               if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
> > +                       DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
> > +
> > +                       /* Enable normal pixel sending for FDI */
> > +                       I915_WRITE(DP_TP_CTL(PORT_E),
> > +                                  DP_TP_CTL_FDI_AUTOTRAIN |
> > +                                  DP_TP_CTL_LINK_TRAIN_NORMAL |
> > +                                  DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> > +                                  DP_TP_CTL_ENABLE);
> > +
> > +                       return;
> > +               }
> > +
> > +               temp = I915_READ(DDI_BUF_CTL(PORT_E));
> > +               temp &= ~DDI_BUF_CTL_ENABLE;
> > +               I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
> > +               POSTING_READ(DDI_BUF_CTL(PORT_E));
> > +
> > +               /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> > +               temp = I915_READ(DP_TP_CTL(PORT_E));
> > +               temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> > +               temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > +               I915_WRITE(DP_TP_CTL(PORT_E), temp);
> > +               POSTING_READ(DP_TP_CTL(PORT_E));
> > +
> > +               intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > +
> > +               rx_ctl_val &= ~FDI_RX_ENABLE;
> > +               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > +               POSTING_READ(_FDI_RXA_CTL);
> > +
> > +               /* Reset FDI_RX_MISC pwrdn lanes */
> > +               temp = I915_READ(_FDI_RXA_MISC);
> > +               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> > +               temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> > +               I915_WRITE(_FDI_RXA_MISC, temp);
> > +               POSTING_READ(_FDI_RXA_MISC);
> > +       }
> > +
> > +       DRM_ERROR("FDI link training failed!\n");
> > +}
> > +
> > +static void hsw_crt_pre_enable(struct intel_encoder *encoder)
> > +{
> > +       hsw_fdi_link_train(encoder->base.crtc);
> > +}
> > +
> >  /* Note: The caller is required to filter out dpms modes not supported by the
> >   * platform. */
> >  static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> > @@ -865,6 +1000,7 @@ void intel_crt_init(struct drm_device *dev)
> >         if (HAS_DDI(dev)) {
> >                 crt->base.get_config = hsw_crt_get_config;
> >                 crt->base.get_hw_state = hsw_crt_get_hw_state;
> > +               crt->base.pre_enable = hsw_crt_pre_enable;
> >         } else {
> >                 crt->base.get_config = intel_crt_get_config;
> >                 crt->base.get_hw_state = intel_crt_get_hw_state;
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index afa1e87c54cc..13abde3e848f 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -211,20 +211,8 @@ void intel_prepare_ddi(struct drm_device *dev)
> >                 intel_prepare_ddi_buffers(dev, port);
> >  }
> >
> > -static const long hsw_ddi_buf_ctl_values[] = {
> > -       DDI_BUF_EMP_400MV_0DB_HSW,
> > -       DDI_BUF_EMP_400MV_3_5DB_HSW,
> > -       DDI_BUF_EMP_400MV_6DB_HSW,
> > -       DDI_BUF_EMP_400MV_9_5DB_HSW,
> > -       DDI_BUF_EMP_600MV_0DB_HSW,
> > -       DDI_BUF_EMP_600MV_3_5DB_HSW,
> > -       DDI_BUF_EMP_600MV_6DB_HSW,
> > -       DDI_BUF_EMP_800MV_0DB_HSW,
> > -       DDI_BUF_EMP_800MV_3_5DB_HSW
> > -};
> > -
> > -static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > -                                   enum port port)
> > +void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > +                            enum port port)
> >  {
> >         uint32_t reg = DDI_BUF_CTL(port);
> >         int i;
> > @@ -246,124 +234,6 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> >   * DDI A (which is used for eDP)
> >   */
> >
> > -void hsw_fdi_link_train(struct drm_crtc *crtc)
> > -{
> > -       struct drm_device *dev = crtc->dev;
> > -       struct drm_i915_private *dev_priv = dev->dev_private;
> > -       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -       u32 temp, i, rx_ctl_val;
> > -
> > -       /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> > -        * mode set "sequence for CRT port" document:
> > -        * - TP1 to TP2 time with the default value
> > -        * - FDI delay to 90h
> > -        *
> > -        * WaFDIAutoLinkSetTimingOverrride:hsw
> > -        */
> > -       I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
> > -                                 FDI_RX_PWRDN_LANE0_VAL(2) |
> > -                                 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> > -
> > -       /* Enable the PCH Receiver FDI PLL */
> > -       rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> > -                    FDI_RX_PLL_ENABLE |
> > -                    FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
> > -       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > -       POSTING_READ(_FDI_RXA_CTL);
> > -       udelay(220);
> > -
> > -       /* Switch from Rawclk to PCDclk */
> > -       rx_ctl_val |= FDI_PCDCLK;
> > -       I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > -
> > -       /* Configure Port Clock Select */
> > -       I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> > -
> > -       /* Start the training iterating through available voltages and emphasis,
> > -        * testing each value twice. */
> > -       for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> > -               /* Configure DP_TP_CTL with auto-training */
> > -               I915_WRITE(DP_TP_CTL(PORT_E),
> > -                                       DP_TP_CTL_FDI_AUTOTRAIN |
> > -                                       DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> > -                                       DP_TP_CTL_LINK_TRAIN_PAT1 |
> > -                                       DP_TP_CTL_ENABLE);
> > -
> > -               /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
> > -                * DDI E does not support port reversal, the functionality is
> > -                * achieved on the PCH side in FDI_RX_CTL, so no need to set the
> > -                * port reversal bit */
> > -               I915_WRITE(DDI_BUF_CTL(PORT_E),
> > -                          DDI_BUF_CTL_ENABLE |
> > -                          ((intel_crtc->config.fdi_lanes - 1) << 1) |
> > -                          hsw_ddi_buf_ctl_values[i / 2]);
> > -               POSTING_READ(DDI_BUF_CTL(PORT_E));
> > -
> > -               udelay(600);
> > -
> > -               /* Program PCH FDI Receiver TU */
> > -               I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
> > -
> > -               /* Enable PCH FDI Receiver with auto-training */
> > -               rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
> > -               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > -               POSTING_READ(_FDI_RXA_CTL);
> > -
> > -               /* Wait for FDI receiver lane calibration */
> > -               udelay(30);
> > -
> > -               /* Unset FDI_RX_MISC pwrdn lanes */
> > -               temp = I915_READ(_FDI_RXA_MISC);
> > -               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> > -               I915_WRITE(_FDI_RXA_MISC, temp);
> > -               POSTING_READ(_FDI_RXA_MISC);
> > -
> > -               /* Wait for FDI auto training time */
> > -               udelay(5);
> > -
> > -               temp = I915_READ(DP_TP_STATUS(PORT_E));
> > -               if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
> > -                       DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
> > -
> > -                       /* Enable normal pixel sending for FDI */
> > -                       I915_WRITE(DP_TP_CTL(PORT_E),
> > -                                  DP_TP_CTL_FDI_AUTOTRAIN |
> > -                                  DP_TP_CTL_LINK_TRAIN_NORMAL |
> > -                                  DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> > -                                  DP_TP_CTL_ENABLE);
> > -
> > -                       return;
> > -               }
> > -
> > -               temp = I915_READ(DDI_BUF_CTL(PORT_E));
> > -               temp &= ~DDI_BUF_CTL_ENABLE;
> > -               I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
> > -               POSTING_READ(DDI_BUF_CTL(PORT_E));
> > -
> > -               /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
> > -               temp = I915_READ(DP_TP_CTL(PORT_E));
> > -               temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> > -               temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > -               I915_WRITE(DP_TP_CTL(PORT_E), temp);
> > -               POSTING_READ(DP_TP_CTL(PORT_E));
> > -
> > -               intel_wait_ddi_buf_idle(dev_priv, PORT_E);
> > -
> > -               rx_ctl_val &= ~FDI_RX_ENABLE;
> > -               I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> > -               POSTING_READ(_FDI_RXA_CTL);
> > -
> > -               /* Reset FDI_RX_MISC pwrdn lanes */
> > -               temp = I915_READ(_FDI_RXA_MISC);
> > -               temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
> > -               temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
> > -               I915_WRITE(_FDI_RXA_MISC, temp);
> > -               POSTING_READ(_FDI_RXA_MISC);
> > -       }
> > -
> > -       DRM_ERROR("FDI link training failed!\n");
> > -}
> > -
> >  static struct intel_encoder *
> >  intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
> >  {
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 82ad84eefc8d..80b34ac31d0a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3858,9 +3858,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> >         if (intel_crtc->config.has_pch_encoder)
> >                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
> >
> > -       if (intel_crtc->config.has_pch_encoder)
> > -               dev_priv->display.fdi_link_train(crtc);
> > -
> >         for_each_encoder_on_crtc(dev, crtc, encoder)
> >                 if (encoder->pre_enable)
> >                         encoder->pre_enable(encoder);
> > @@ -11120,7 +11117,6 @@ static void intel_init_display(struct drm_device *dev)
> >                         dev_priv->display.modeset_global_resources =
> >                                 ivb_modeset_global_resources;
> >                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> > -                       dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> >                         dev_priv->display.write_eld = haswell_write_eld;
> >                         dev_priv->display.modeset_global_resources =
> >                                 haswell_modeset_global_resources;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 1c093e71db7d..7f1d7f675953 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -668,11 +668,12 @@ void intel_crt_init(struct drm_device *dev);
> >
> >  /* intel_ddi.c */
> >  void intel_prepare_ddi(struct drm_device *dev);
> > -void hsw_fdi_link_train(struct drm_crtc *crtc);
> >  void intel_ddi_init(struct drm_device *dev, enum port port);
> >  enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
> >  bool intel_ddi_get_port_state(struct intel_encoder *encoder, enum pipe *pipe,
> >                               enum port port);
> > +void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> > +                            enum port port);
> >  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
> >  void intel_ddi_pll_init(struct drm_device *dev);
> >  void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 47/66] drm/i915: Move pch fifo underrun report enabling to hsw_crt_pre_enable

[Daniel Vetter]

On Thu, May 22, 2014 at 05:38:13PM -0300, Paulo Zanoni wrote:
> 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > With this all the pch pre-enable work has been moved into the special
> > hsw crt encoder functions.
> 
> For the same reasons I gave in the other patches, I'm not convinced
> this is an improvement to our code. It looks like we're just breaking
> the abstraction exploiting the fact that CRT is the only FDI/PCH
> output on Haswell. Now the HSW code will be significantly different
> from the ILK/SNB/HSW code, and I really think this can be confusing to
> people reading the code. I really think we shouldn't hide things
> aren't specific to CRT inside CRT code.

See my other mail, imo this does _not_ break the abstraction, but actually
fix it. If you look at the crtc/encoder split, the thing that connects
these two is the crossbar. So we should put the code into crtc/encoder
callbacks so that roughly everything before the crossbar is in crtc
callbacks, and everything after it is in encoder callbacks.

Of course there will be some small exceptions, e.g. a lot of the ddi port
handling (which is after the crossbar) is in crtc code. But that makes imo
sense since ddi ports are so nicely unfified between dp, hdmi and fdi.

> Since on this series we're basically disagreeing on our opinions on
> which coding style is the better, I think we should ask the other
> developers to give their opinion too :)

I'm not sure more people will help here. But this is an area I'm often
struggling on review. E.g. Ben's full ppgtt patches treat the aliasing
ppgtt on gen6 in many places like a full ppgtt. Which makes sense since
they are both called ppgtt and share a lot of the same low-level code.

But from a functional pov the aliasing ppgtt is something completely
different from full ppgtt: The first is just a fancy way to write ptes,
the 2nd is fundamentally different wrt how buffer objects get mapped into
the gpu address space.

And I'm pretty sure I've made noises like this back when we've merged the
original hsw support ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS

[Paulo Zanoni]

2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Keeping track of the power domains is a bit messy since crtc->active
> is currently updated by the platform hooks, but we need to be aware of
> which state transition exactly is going on. Maybe we simply need to
> shovel all the power domain handling down into platform code to
> simplify this. But doing that requires some more auditing since
> currently the ->mode_set callbacks still read some random registers
> (to e.g. figure out the reference clocks).
>
> Also note that intel_crtc_update_dpms is always call first/last even
> for encoders which have their own dpms functions. Hence we really only
> need to update this place here.
>
> Being a quick "does it blow up?" run not really tested yet.

Shouldn't we put some "if (is hsw or newer)" here? I was assuming your
series did not care about the SNB code paths, and we do have SNB
runtime PM support.

I also agree with Jesse's plans to push things to crtc_enable/disable,
then remove this code and the code from modeset_global_resources. But
if that's complicated, for now the current solution is fine.

>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e0bd0f94e43e..1b5d6b099b37 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4478,16 +4478,34 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
>         struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>         struct intel_encoder *intel_encoder;
> +       enum intel_display_power_domain domain;
> +       unsigned long domains;
>         bool enable = false;
>
>         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
>                 enable |= intel_encoder->connectors_active;
>
> -       if (enable)
> -               dev_priv->display.crtc_enable(crtc);
> -       else
> -               dev_priv->display.crtc_disable(crtc);
> +       if (enable) {
> +               if (!intel_crtc->active) {
> +                       domains = get_crtc_power_domains(crtc);
> +                       for_each_power_domain(domain, domains)
> +                               intel_display_power_get(dev_priv, domain);
> +                       intel_crtc->enabled_power_domains = domains;
> +
> +                       dev_priv->display.crtc_enable(crtc);
> +               }
> +       } else {
> +               if (intel_crtc->active) {
> +                       dev_priv->display.crtc_disable(crtc);
> +
> +                       domains = intel_crtc->enabled_power_domains;
> +                       for_each_power_domain(domain, domains)
> +                               intel_display_power_put(dev_priv, domain);
> +                       intel_crtc->enabled_power_domains = 0;
> +               }
> +       }
>
>         intel_crtc_update_sarea(crtc, enable);
>  }
> --
> 1.8.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

[Jesse Barnes]

On Thu, 22 May 2014 23:57:02 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Thu, May 22, 2014 at 05:28:05PM -0300, Paulo Zanoni wrote:
> > 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > > The pch encoder case really isn't anything generic on hsw:
> > > - It's for the vga port only and
> > > - the vga port does only exist on some hsw platforms.
> > >
> > > Imo it helps the generic code flow a lot if we shovel all this into
> > > hsw specific enable/disable hooks. A bonus is that some of our largest
> > > files (intel_ddi.c and intel_display.c) will lose a pile of really big
> > > functions.
> > >
> > > Step one is to move the fdi link training code.
> > 
> > I don't think that helps much, since the other fdi link train code is
> > still at intel_display.c, and even if the only thing that needs fdi
> > link training on HSW is CRT, fdi link training is really _not_ a CRT
> > thing. So IMHO we're breaking an abstraction here by putting fdi link
> > training in CRT code. Also, the fact that HSW+ won't be using
> > dev_priv->display.fdi_link_train will makes things even more confusing
> > for people reading our code.
> > 
> > I'd really prefer if we merge
> > http://patchwork.freedesktop.org/patch/24019/ instead. Or something
> > based on that.
> 
> Well my idea with all this was that even on hsw vga on the pch is a bit
> the special case, and on bdw+ it's completely gone. So taking this out of
> the common modeset code should help bdw+ a bit since now the modeset
> sequence and our code really nicely align.
> 
> Also with ilk-ivb having the fdi code in the crtc functions made a lot of
> sense since the big crossbar was in the pch. So doing everything up to the
> pch crossbar, including all the fdi handling in crtc code, and everything
> after that in encoder callbacks.
> 
> But on hsw+ we have the big crossbar on the cpu side, between the
> transcoders and the ddi ports. So from a functional pov it makes much more
> sense imo to have all the pipe/transcoder code in the crtc, and all the
> ddi handling code in encoder callbacks. The pch and fdi link that hang off
> ddi port E work more like a drm_bridge (but we don't need that since the
> lpt pch will never be used outside of intel platforms).
> 
> So with this example, grouping all the fdi code together only groups
> functions by their name. But moving the hsw fdi stuff into the crt encoder
> groups the code by the behaviour of the hardware. And that's massively
> different betweent ivb and hsw.
> 
> I hope this explains a bit my thinking here.

I think I agree with Paulo here.  FDI happens to be only used for VGA
on HSW, but it's theoretically possible to use it for other stuff on
the PCH side, so keeping it under has_pch_encoder in the platform
independent code paths makes sense.

But a nice compromise would be to split out the FDI code as Paulo
suggested; that would get it out of intel_display.c and maybe make for
less confusion.

On top of that, we could export the FDI training stuff from there and
push the training calls as needed into the ports, like you've done with
the CRT here, but overall I think the training code itself should live
separately from the port code, since who knows what funky things may be
coming.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 46/66] drm/i915: Move hsw_fdi_link_train into intel_crt.c

[Daniel Vetter]

On Tue, May 27, 2014 at 10:31:43AM -0700, Jesse Barnes wrote:
> On Thu, 22 May 2014 23:57:02 +0200
> Daniel Vetter <daniel@ffwll.ch> wrote:
> 
> > On Thu, May 22, 2014 at 05:28:05PM -0300, Paulo Zanoni wrote:
> > > 2014-04-24 18:55 GMT-03:00 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > > > The pch encoder case really isn't anything generic on hsw:
> > > > - It's for the vga port only and
> > > > - the vga port does only exist on some hsw platforms.
> > > >
> > > > Imo it helps the generic code flow a lot if we shovel all this into
> > > > hsw specific enable/disable hooks. A bonus is that some of our largest
> > > > files (intel_ddi.c and intel_display.c) will lose a pile of really big
> > > > functions.
> > > >
> > > > Step one is to move the fdi link training code.
> > > 
> > > I don't think that helps much, since the other fdi link train code is
> > > still at intel_display.c, and even if the only thing that needs fdi
> > > link training on HSW is CRT, fdi link training is really _not_ a CRT
> > > thing. So IMHO we're breaking an abstraction here by putting fdi link
> > > training in CRT code. Also, the fact that HSW+ won't be using
> > > dev_priv->display.fdi_link_train will makes things even more confusing
> > > for people reading our code.
> > > 
> > > I'd really prefer if we merge
> > > http://patchwork.freedesktop.org/patch/24019/ instead. Or something
> > > based on that.
> > 
> > Well my idea with all this was that even on hsw vga on the pch is a bit
> > the special case, and on bdw+ it's completely gone. So taking this out of
> > the common modeset code should help bdw+ a bit since now the modeset
> > sequence and our code really nicely align.
> > 
> > Also with ilk-ivb having the fdi code in the crtc functions made a lot of
> > sense since the big crossbar was in the pch. So doing everything up to the
> > pch crossbar, including all the fdi handling in crtc code, and everything
> > after that in encoder callbacks.
> > 
> > But on hsw+ we have the big crossbar on the cpu side, between the
> > transcoders and the ddi ports. So from a functional pov it makes much more
> > sense imo to have all the pipe/transcoder code in the crtc, and all the
> > ddi handling code in encoder callbacks. The pch and fdi link that hang off
> > ddi port E work more like a drm_bridge (but we don't need that since the
> > lpt pch will never be used outside of intel platforms).
> > 
> > So with this example, grouping all the fdi code together only groups
> > functions by their name. But moving the hsw fdi stuff into the crt encoder
> > groups the code by the behaviour of the hardware. And that's massively
> > different betweent ivb and hsw.
> > 
> > I hope this explains a bit my thinking here.
> 
> I think I agree with Paulo here.  FDI happens to be only used for VGA
> on HSW, but it's theoretically possible to use it for other stuff on
> the PCH side, so keeping it under has_pch_encoder in the platform
> independent code paths makes sense.

There is simply no silicon with anything but a VGA encoder on the pch. And
even though the hw engineers have kept all the register at the same place,
there's also no cross bar any more, and also no 2nd pipe. The lpt pch
really is just a fancy transcoder, and imo should be treated like that.

> But a nice compromise would be to split out the FDI code as Paulo
> suggested; that would get it out of intel_display.c and maybe make for
> less confusion.
> 
> On top of that, we could export the FDI training stuff from there and
> push the training calls as needed into the ports, like you've done with
> the CRT here, but overall I think the training code itself should live
> separately from the port code, since who knows what funky things may be
> coming.

VGA is dead, also fdi seems to have gone. The way to do transcoders for
specific produts seems to either be with (e)DP or with mipi.

I'm not against extracting all the fdi code into an intel_fdi.c file
really, but since there's not a lot of shared code I don't really see the
point all that much. For me the metric to measure whether a new source
file works is the number of exports and interactions between different
pieces of code.

But like you've said, this code shuffling here doesn't really prevent
anyone from doing intel_pch.c ..
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS

[Daniel Vetter]

On Thu, Apr 24, 2014 at 11:55:42PM +0200, Daniel Vetter wrote:
> Keeping track of the power domains is a bit messy since crtc->active
> is currently updated by the platform hooks, but we need to be aware of
> which state transition exactly is going on. Maybe we simply need to
> shovel all the power domain handling down into platform code to
> simplify this. But doing that requires some more auditing since
> currently the ->mode_set callbacks still read some random registers
> (to e.g. figure out the reference clocks).
> 
> Also note that intel_crtc_update_dpms is always call first/last even
> for encoders which have their own dpms functions. Hence we really only
> need to update this place here.
> 
> Being a quick "does it blow up?" run not really tested yet.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Ok, I've simply gone ahead and merged this with a !HAS_DDI check so that I
can unblock runtime pm for dpms.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e0bd0f94e43e..1b5d6b099b37 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4478,16 +4478,34 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *intel_encoder;
> +	enum intel_display_power_domain domain;
> +	unsigned long domains;
>  	bool enable = false;
>  
>  	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
>  		enable |= intel_encoder->connectors_active;
>  
> -	if (enable)
> -		dev_priv->display.crtc_enable(crtc);
> -	else
> -		dev_priv->display.crtc_disable(crtc);
> +	if (enable) {
> +		if (!intel_crtc->active) {
> +			domains = get_crtc_power_domains(crtc);
> +			for_each_power_domain(domain, domains)
> +				intel_display_power_get(dev_priv, domain);
> +			intel_crtc->enabled_power_domains = domains;
> +
> +			dev_priv->display.crtc_enable(crtc);
> +		}
> +	} else {
> +		if (intel_crtc->active) {
> +			dev_priv->display.crtc_disable(crtc);
> +
> +			domains = intel_crtc->enabled_power_domains;
> +			for_each_power_domain(domain, domains)
> +				intel_display_power_put(dev_priv, domain);
> +			intel_crtc->enabled_power_domains = 0;
> +		}
> +	}
>  
>  	intel_crtc_update_sarea(crtc, enable);
>  }
> -- 
> 1.8.1.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch