From mboxrd@z Thu Jan  1 00:00:00 1970
From: Deepak S <deepak.s@linux.intel.com>
Subject: Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR
 fetch into init_clock_gating
Date: Tue, 27 May 2014 17:41:57 +0530
Message-ID: <5384810D.9040606@linux.intel.com>
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To: =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>, Daniel Vetter <daniel@ffwll.ch>
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On Tuesday 27 May 2014 05:29 PM, Ville Syrj=E4l=E4 wrote:
> On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
>> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
>>> deepak.s@linux.intel.com writes:
>>>
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> [vsyrjala: Fix merge fubmle where the code ended up in
>>>> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
>>>> Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
>>>> Acked-by: Ben Widawsky <ben@bwidawsk.net>
>>>> ---
>>>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>>   1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in=
tel_pm.c
>>>> index 08dcdc5..0b73a6d 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_de=
vice *dev)
>>>>   		   GEN6_RP_UP_BUSY_AVG |
>>>>   		   GEN6_RP_DOWN_IDLE_AVG);
>>>>   =

>>>> +	/* ToDo: Update the mem freq based on latest spec [CHV]*/
>>> Please do and consider fixing the vlv decoding. It seems to be off
>>> too.
>> Poke about this one here. Iirc the situation on vlv is simply terminal
>> confusion, and iirc the current code matches reality of shipping vbiosen,
>> but not any spec.
> Yeah changed back here:
>
> commit f6d519481b662d9fc52836e6e6107520f03e0122
> Author: Deepak S <deepak.s@linux.intel.com>
> Date:   Thu Apr 3 21:01:28 2014 +0530
>
>      Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
>      =

>      As per the inputs provided by hardware team  we still use DDR
>      Rates as 0,1=3D800, 2=3D1066, 3=3D1333.
>      With this change, Turbo freqs used on current machines matches.
>
>
> I think what we need is a comment there which states why
> we're going against the spec, just to avoid future confusion
> and someone accidentally changing it back again.
>
>> I hope we're bettter for chv.
> One can dream.

Problem is the spec is not update to latest. Based on the communication fro=
m the HW team i update the proper value.
For CHV, I have updated based on the values i got from HW team.