From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Richter Subject: [PATCH] Align i830 watermark to cache lines Date: Mon, 02 Jun 2014 12:34:59 +0200 Message-ID: <538C5353.40001@rus.uni-stuttgart.de> References: <53761A88.1060608@math.tu-berlin.de> <20140516144104.GE3473@nuc-i3427.alporthouse.com> <20140516150953.GN8790@phenom.ffwll.local> <20140516160454.GT27580@intel.com> <23914_1400259040_537641E0_23914_9298_1_20140516165034.GT8790@phenom.ffwll.local> <5387A473.5020102@rus.uni-stuttgart.de> <20140602082705.GJ19050@phenom.ffwll.local> Reply-To: richter@rus.uni-stuttgart.de Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------070701070309000204070208" Return-path: Received: from hydra.rus.uni-stuttgart.de (hydra.rus.uni-stuttgart.de [129.69.192.3]) by gabe.freedesktop.org (Postfix) with ESMTP id 69B3E6E519 for ; Mon, 2 Jun 2014 03:35:09 -0700 (PDT) In-Reply-To: <20140602082705.GJ19050@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --------------070701070309000204070208 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi folks, as by discussion, the problem with the i830 watermark problems is likely that the 830 requires the number of entries in the buffer to be a multiple of the cache line size. I provide hereby a small patch against intel_pm.c that performs the alignment for GEN2 chips. Tested on the Fujitsu S6010 and R31, seems to work fine here and generates reasonable watermarks that do not flicker. What is a bit unsatisfactory is that, due to the nature of the patch, the number of entries in the buffer is always rounded up (necessarily, to be conservative), even though for all practical configurations, the rounded up size is too large to fit into the buffer, and thus the rounding direction is "round down" instead of "round up" for all realistic settings. Anyhow, the stuff works. Greetings, Thomas --------------070701070309000204070208 Content-Type: text/x-patch; name="0001-Align-i830-watermark-to-cache-lines.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0001-Align-i830-watermark-to-cache-lines.patch" >>From ee1210a1f49abaddc2c6c46cfb521db6ab08c261 Mon Sep 17 00:00:00 2001 From: thor Date: Sun, 1 Jun 2014 18:33:20 +0200 Subject: [PATCH] Align i830 watermark to cache lines. Signed-off-by: thor --- drivers/gpu/drm/i915/intel_pm.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1840d15..fbfd57c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1489,6 +1489,22 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); } +static int round_to_lines(int watermark, int fifo_size, int line_size) +{ + int entries = fifo_size - watermark; + + if (entries < 0) + entries = 0; + + entries = DIV_ROUND_UP(entries, line_size); + while (entries > fifo_size) + entries -= line_size; + + watermark = fifo_size - line_size; + + return watermark; +} + static void i9xx_update_wm(struct drm_crtc *unused_crtc) { struct drm_device *dev = unused_crtc->dev; @@ -1520,6 +1536,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, latency_ns); + + if (IS_GEN2(dev)) + planea_wm = round_to_lines(planea_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + enabled = crtc; } else planea_wm = fifo_size - wm_info->guard_size; @@ -1536,6 +1558,12 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, wm_info, fifo_size, cpp, latency_ns); + + if (IS_GEN2(dev)) + planeb_wm = round_to_lines(planeb_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + if (enabled == NULL) enabled = crtc; else @@ -1631,16 +1659,24 @@ static void i845_update_wm(struct drm_crtc *unused_crtc) const struct drm_display_mode *adjusted_mode; uint32_t fwater_lo; int planea_wm; + int fifo_size; crtc = single_enabled_crtc(dev); if (crtc == NULL) return; adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; + fifo_size = dev_priv->display.get_fifo_size(dev, 0); planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, &i845_wm_info, - dev_priv->display.get_fifo_size(dev, 0), + fifo_size, 4, latency_ns); + + planea_wm = round_to_lines(planea_wm, + fifo_size, + I830_FIFO_LINE_SIZE); + + fwater_lo = I915_READ(FW_BLC) & ~0xfff; fwater_lo |= (3<<8) | planea_wm; -- 1.7.10.4 --------------070701070309000204070208 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --------------070701070309000204070208--