[PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec

[PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec

[Imre Deak]

These opcodes are not specific for an endpoint, but are the same for all
endpoints. So rename them accordingly, using the name the VLV2 sideband
HAS uses. Also move the macros to the .c file, since they aren't used
anywhere else.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       |  5 ----
 drivers/gpu/drm/i915/intel_sideband.c | 51 ++++++++++++++++++++---------------
 2 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac90786..3d437d1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -484,9 +484,6 @@
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC				0x11
 
-#define PUNIT_OPCODE_REG_READ			6
-#define PUNIT_OPCODE_REG_WRITE			7
-
 #define PUNIT_REG_DSPFREQ			0x36
 #define   DSPFREQSTAT_SHIFT			30
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
@@ -580,8 +577,6 @@ enum punit_power_well {
  * Note: digital port B is DDI0, digital pot C is DDI1
  */
 #define DPIO_DEVFN			0
-#define DPIO_OPCODE_REG_WRITE		1
-#define DPIO_OPCODE_REG_READ		0
 
 #define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
 #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index b1a5514..f3909d5 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -29,12 +29,21 @@
  * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
  * VLV_VLV2_PUNIT_HAS_0.8.docx
  */
+
+/* Standard MMIO read, non-posted */
+#define SB_MRD_NP	0x00
+/* Standard MMIO write, non-posted */
+#define SB_MWR_NP	0x01
+/* Private register read, double-word addressing, non-posted */
+#define SB_CRRDDA_NP	0x06
+/* Private register write, double-word addressing, non-posted */
+#define SB_CRWRDA_NP	0x07
+
 static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
 			   u32 port, u32 opcode, u32 addr, u32 *val)
 {
 	u32 cmd, be = 0xf, bar = 0;
-	bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
-			opcode == DPIO_OPCODE_REG_READ);
+	bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
 
 	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
 		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
@@ -74,7 +83,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
 
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
-			PUNIT_OPCODE_REG_READ, addr, &val);
+			SB_CRRDDA_NP, addr, &val);
 	mutex_unlock(&dev_priv->dpio_lock);
 
 	return val;
@@ -86,7 +95,7 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
 
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
-			PUNIT_OPCODE_REG_WRITE, addr, &val);
+			SB_CRWRDA_NP, addr, &val);
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
@@ -95,7 +104,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
 	u32 val = 0;
 
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
-			PUNIT_OPCODE_REG_READ, reg, &val);
+			SB_CRRDDA_NP, reg, &val);
 
 	return val;
 }
@@ -103,7 +112,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
-			PUNIT_OPCODE_REG_WRITE, reg, &val);
+			SB_CRWRDA_NP, reg, &val);
 }
 
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
@@ -114,7 +123,7 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 
 	mutex_lock(&dev_priv->dpio_lock);
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
-			PUNIT_OPCODE_REG_READ, addr, &val);
+			SB_CRRDDA_NP, addr, &val);
 	mutex_unlock(&dev_priv->dpio_lock);
 
 	return val;
@@ -124,56 +133,56 @@ u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
-			PUNIT_OPCODE_REG_READ, reg, &val);
+			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
-			PUNIT_OPCODE_REG_WRITE, reg, &val);
+			SB_CRWRDA_NP, reg, &val);
 }
 
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
-			PUNIT_OPCODE_REG_READ, reg, &val);
+			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
-			PUNIT_OPCODE_REG_WRITE, reg, &val);
+			SB_CRWRDA_NP, reg, &val);
 }
 
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
-			PUNIT_OPCODE_REG_READ, reg, &val);
+			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
-			PUNIT_OPCODE_REG_WRITE, reg, &val);
+			SB_CRWRDA_NP, reg, &val);
 }
 
 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
-			PUNIT_OPCODE_REG_READ, reg, &val);
+			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
-			PUNIT_OPCODE_REG_WRITE, reg, &val);
+			SB_CRWRDA_NP, reg, &val);
 }
 
 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
@@ -181,7 +190,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 	u32 val = 0;
 
 	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
-			DPIO_OPCODE_REG_READ, reg, &val);
+			SB_MRD_NP, reg, &val);
 
 	/*
 	 * FIXME: There might be some registers where all 1's is a valid value,
@@ -196,7 +205,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
 {
 	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
-			DPIO_OPCODE_REG_WRITE, reg, &val);
+			SB_MWR_NP, reg, &val);
 }
 
 /* SBI access */
@@ -261,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
-					DPIO_OPCODE_REG_READ, reg, &val);
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
+			reg, &val);
 	return val;
 }
 
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
-					DPIO_OPCODE_REG_WRITE, reg, &val);
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
+			reg, &val);
 }
-- 
1.8.4

[PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Imre Deak]

So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the initial modeset,
where the BIOS-programmed values happened to work, but after resuming
from s0ix these registers are reset and failing to program them results
in a blank screen.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index f3909d5..01d841e 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
 {
 	u32 val = 0;
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
 			reg, &val);
 	return val;
 }
 
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
 			reg, &val);
 }
-- 
1.8.4

Re: [PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec

[Jesse Barnes]

On Mon, 19 May 2014 11:41:17 +0300
Imre Deak <imre.deak@intel.com> wrote:

> These opcodes are not specific for an endpoint, but are the same for all
> endpoints. So rename them accordingly, using the name the VLV2 sideband
> HAS uses. Also move the macros to the .c file, since they aren't used
> anywhere else.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h       |  5 ----
>  drivers/gpu/drm/i915/intel_sideband.c | 51 ++++++++++++++++++++---------------
>  2 files changed, 30 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac90786..3d437d1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -484,9 +484,6 @@
>  /* See configdb bunit SB addr map */
>  #define BUNIT_REG_BISOC				0x11
>  
> -#define PUNIT_OPCODE_REG_READ			6
> -#define PUNIT_OPCODE_REG_WRITE			7
> -
>  #define PUNIT_REG_DSPFREQ			0x36
>  #define   DSPFREQSTAT_SHIFT			30
>  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> @@ -580,8 +577,6 @@ enum punit_power_well {
>   * Note: digital port B is DDI0, digital pot C is DDI1
>   */
>  #define DPIO_DEVFN			0
> -#define DPIO_OPCODE_REG_WRITE		1
> -#define DPIO_OPCODE_REG_READ		0
>  
>  #define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
>  #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index b1a5514..f3909d5 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -29,12 +29,21 @@
>   * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
>   * VLV_VLV2_PUNIT_HAS_0.8.docx
>   */
> +
> +/* Standard MMIO read, non-posted */
> +#define SB_MRD_NP	0x00
> +/* Standard MMIO write, non-posted */
> +#define SB_MWR_NP	0x01
> +/* Private register read, double-word addressing, non-posted */
> +#define SB_CRRDDA_NP	0x06
> +/* Private register write, double-word addressing, non-posted */
> +#define SB_CRWRDA_NP	0x07
> +
>  static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
>  			   u32 port, u32 opcode, u32 addr, u32 *val)
>  {
>  	u32 cmd, be = 0xf, bar = 0;
> -	bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
> -			opcode == DPIO_OPCODE_REG_READ);
> +	bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
>  
>  	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
>  		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> @@ -74,7 +83,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
> -			PUNIT_OPCODE_REG_READ, addr, &val);
> +			SB_CRRDDA_NP, addr, &val);
>  	mutex_unlock(&dev_priv->dpio_lock);
>  
>  	return val;
> @@ -86,7 +95,7 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
> -			PUNIT_OPCODE_REG_WRITE, addr, &val);
> +			SB_CRWRDA_NP, addr, &val);
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> @@ -95,7 +104,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
>  	u32 val = 0;
>  
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> -			PUNIT_OPCODE_REG_READ, reg, &val);
> +			SB_CRRDDA_NP, reg, &val);
>  
>  	return val;
>  }
> @@ -103,7 +112,7 @@ u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
>  void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> -			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +			SB_CRWRDA_NP, reg, &val);
>  }
>  
>  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> @@ -114,7 +123,7 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
> -			PUNIT_OPCODE_REG_READ, addr, &val);
> +			SB_CRRDDA_NP, addr, &val);
>  	mutex_unlock(&dev_priv->dpio_lock);
>  
>  	return val;
> @@ -124,56 +133,56 @@ u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
> -			PUNIT_OPCODE_REG_READ, reg, &val);
> +			SB_CRRDDA_NP, reg, &val);
>  	return val;
>  }
>  
>  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
> -			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +			SB_CRWRDA_NP, reg, &val);
>  }
>  
>  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
> -			PUNIT_OPCODE_REG_READ, reg, &val);
> +			SB_CRRDDA_NP, reg, &val);
>  	return val;
>  }
>  
>  void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
> -			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +			SB_CRWRDA_NP, reg, &val);
>  }
>  
>  u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
> -			PUNIT_OPCODE_REG_READ, reg, &val);
> +			SB_CRRDDA_NP, reg, &val);
>  	return val;
>  }
>  
>  void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
> -			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +			SB_CRWRDA_NP, reg, &val);
>  }
>  
>  u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
> -			PUNIT_OPCODE_REG_READ, reg, &val);
> +			SB_CRRDDA_NP, reg, &val);
>  	return val;
>  }
>  
>  void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
> -			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +			SB_CRWRDA_NP, reg, &val);
>  }
>  
>  u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> @@ -181,7 +190,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
>  	u32 val = 0;
>  
>  	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> -			DPIO_OPCODE_REG_READ, reg, &val);
> +			SB_MRD_NP, reg, &val);
>  
>  	/*
>  	 * FIXME: There might be some registers where all 1's is a valid value,
> @@ -196,7 +205,7 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
>  void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
>  {
>  	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> -			DPIO_OPCODE_REG_WRITE, reg, &val);
> +			SB_MWR_NP, reg, &val);
>  }
>  
>  /* SBI access */
> @@ -261,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> -					DPIO_OPCODE_REG_READ, reg, &val);
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> +			reg, &val);
>  	return val;
>  }
>  
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
> -					DPIO_OPCODE_REG_WRITE, reg, &val);
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> +			reg, &val);
>  }

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Jesse Barnes]

On Mon, 19 May 2014 11:41:18 +0300
Imre Deak <imre.deak@intel.com> wrote:

> So far we used the wrong opcodes to access the DSI registers, so the
> register writes during DSI programming didn't actually succeed and left
> the registers unchanged. This wasn't a problem for the initial modeset,
> where the BIOS-programmed values happened to work, but after resuming
> from s0ix these registers are reset and failing to program them results
> in a blank screen.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index f3909d5..01d841e 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
>  			reg, &val);
>  	return val;
>  }
>  
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
>  			reg, &val);
>  }

Nice find... is this documented somewhere so we can put a reference
in?  Or is it in the Punit HAS somewhere already and we just missed it?

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Imre Deak]

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On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 11:41:18 +0300
> Imre Deak <imre.deak@intel.com> wrote:
> 
> > So far we used the wrong opcodes to access the DSI registers, so the
> > register writes during DSI programming didn't actually succeed and left
> > the registers unchanged. This wasn't a problem for the initial modeset,
> > where the BIOS-programmed values happened to work, but after resuming
> > from s0ix these registers are reset and failing to program them results
> > in a blank screen.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > index f3909d5..01d841e 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> >  {
> >  	u32 val = 0;
> > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> >  			reg, &val);
> >  	return val;
> >  }
> >  
> >  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> >  {
> > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> >  			reg, &val);
> >  }
> 
> Nice find... is this documented somewhere so we can put a reference
> in?  Or is it in the Punit HAS somewhere already and we just missed it?

I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
this file with a reference to it.

--Imre


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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Jesse Barnes]

On Mon, 19 May 2014 18:10:18 +0300
Imre Deak <imre.deak@intel.com> wrote:

> On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
> > On Mon, 19 May 2014 11:41:18 +0300
> > Imre Deak <imre.deak@intel.com> wrote:
> > 
> > > So far we used the wrong opcodes to access the DSI registers, so the
> > > register writes during DSI programming didn't actually succeed and left
> > > the registers unchanged. This wasn't a problem for the initial modeset,
> > > where the BIOS-programmed values happened to work, but after resuming
> > > from s0ix these registers are reset and failing to program them results
> > > in a blank screen.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > > index f3909d5..01d841e 100644
> > > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> > >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> > >  {
> > >  	u32 val = 0;
> > > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> > > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> > >  			reg, &val);
> > >  	return val;
> > >  }
> > >  
> > >  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> > >  {
> > > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> > > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> > >  			reg, &val);
> > >  }
> > 
> > Nice find... is this documented somewhere so we can put a reference
> > in?  Or is it in the Punit HAS somewhere already and we just missed it?
> 
> I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
> this file with a reference to it.

Cool, this one has my
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
then too.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Daniel Vetter]

On Mon, May 19, 2014 at 08:33:16AM -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 18:10:18 +0300
> Imre Deak <imre.deak@intel.com> wrote:
> 
> > On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
> > > On Mon, 19 May 2014 11:41:18 +0300
> > > Imre Deak <imre.deak@intel.com> wrote:
> > > 
> > > > So far we used the wrong opcodes to access the DSI registers, so the
> > > > register writes during DSI programming didn't actually succeed and left
> > > > the registers unchanged. This wasn't a problem for the initial modeset,
> > > > where the BIOS-programmed values happened to work, but after resuming
> > > > from s0ix these registers are reset and failing to program them results
> > > > in a blank screen.
> > > > 
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > > > index f3909d5..01d841e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > > > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> > > >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> > > >  {
> > > >  	u32 val = 0;
> > > > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> > > > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> > > >  			reg, &val);
> > > >  	return val;
> > > >  }
> > > >  
> > > >  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> > > >  {
> > > > -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> > > > +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> > > >  			reg, &val);
> > > >  }
> > > 
> > > Nice find... is this documented somewhere so we can put a reference
> > > in?  Or is it in the Punit HAS somewhere already and we just missed it?
> > 
> > I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
> > this file with a reference to it.
> 
> Cool, this one has my
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> then too.

Both patches merged, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Jani Nikula]

On Mon, 19 May 2014, Imre Deak <imre.deak@intel.com> wrote:
> So far we used the wrong opcodes to access the DSI registers, so the
> register writes during DSI programming didn't actually succeed and left
> the registers unchanged. This wasn't a problem for the initial modeset,
> where the BIOS-programmed values happened to work, but after resuming
> from s0ix these registers are reset and failing to program them results
> in a blank screen.

Shobhit, this was already merged, did you have a chance to test it?

Jani.


>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index f3909d5..01d841e 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
>  {
>  	u32 val = 0;
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
>  			reg, &val);
>  	return val;
>  }
>  
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>  {
> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
>  			reg, &val);
>  }
> -- 
> 1.8.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

[Kumar, Shobhit]

On 5/26/2014 6:22 PM, Jani Nikula wrote:
> On Mon, 19 May 2014, Imre Deak <imre.deak@intel.com> wrote:
>> So far we used the wrong opcodes to access the DSI registers, so the
>> register writes during DSI programming didn't actually succeed and left
>> the registers unchanged. This wasn't a problem for the initial modeset,
>> where the BIOS-programmed values happened to work, but after resuming
>> from s0ix these registers are reset and failing to program them results
>> in a blank screen.
>
> Shobhit, this was already merged, did you have a chance to test it?
>

Sorry just saw this today. Yeah I have pulled this in my test tree and 
suspend/resume was working perfect, but then I was not doing display 
powergate. In the internal code though S0ix was implemented. I will 
double check if the internal code had correct opcodes and somehow wrong 
opcodes trickled into intel-gfx. As of now looks okay and works fine for me.

Regards
Shobhit

> Jani.
>
>
>>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index f3909d5..01d841e 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>>   u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
>>   {
>>   	u32 val = 0;
>> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
>> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
>>   			reg, &val);
>>   	return val;
>>   }
>>
>>   void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
>>   {
>> -	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
>> +	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
>>   			reg, &val);
>>   }
>> --
>> 1.8.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>