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From: Thomas Richter <richter@rus.uni-stuttgart.de>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] Check for a min level when computing the watermark.
Date: Sun, 08 Jun 2014 23:29:01 +0200	[thread overview]
Message-ID: <5394D59D.60703@rus.uni-stuttgart.de> (raw)
In-Reply-To: <20140606200814.GH27580@intel.com>

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Dear intel experts,

the attached patch is a minimally invasive modification of the watermark 
computation for the 830GM chipset graphics. It adds a minimum watermark 
level to test against. The minimum value is zero for all other families 
of the intel chipset graphics, thus causing no change there.

What is still strange is that the default watermark level is only used 
if the watermark level computation returns a value below zero, though 
values *below* the default value are acceptable as long as the are above 
or equal to zero. Anyhow, I keep it like this for the time being to 
avoid breaking anything.

Greetings,
	Thomas


[-- Attachment #2: 0001-Added-a-min-watermark-level.patch --]
[-- Type: text/x-patch, Size: 5544 bytes --]

>From 4ff44b36c3ca8ac0255700aaa8999e75efbf9598 Mon Sep 17 00:00:00 2001
From: thor <thor@math.tu-berlin.de>
Date: Sat, 7 Jun 2014 22:23:16 +0200
Subject: [PATCH] Added a min watermark level.

Signed-off-by: thor <thor@math.tu-berlin.de>
---
 drivers/gpu/drm/i915/i915_reg.h  |    1 +
 drivers/gpu/drm/i915/intel_drv.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c  |   16 ++++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..442240b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3897,6 +3897,7 @@ enum punit_power_well {
 #define I915_FIFO_SIZE		95
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
+#define I830_MIN_WM		8
 
 #define VALLEYVIEW_MAX_WM	0xff
 #define G4X_MAX_WM		0x3f
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 78d4124..16d2f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -458,6 +458,7 @@ struct intel_plane {
 
 struct intel_watermark_params {
 	unsigned long fifo_size;
+	unsigned long min_wm;
 	unsigned long max_wm;
 	unsigned long default_wm;
 	unsigned long guard_size;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f83d1ff..ac8a832 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -866,6 +866,7 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -873,6 +874,7 @@ static const struct intel_watermark_params pineview_display_wm = {
 };
 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 	.fifo_size = PINEVIEW_DISPLAY_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_MAX_WM,
 	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 	.guard_size = PINEVIEW_GUARD_WM,
@@ -880,6 +882,7 @@ static const struct intel_watermark_params pineview_display_hplloff_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -887,6 +890,7 @@ static const struct intel_watermark_params pineview_cursor_wm = {
 };
 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 	.fifo_size = PINEVIEW_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = PINEVIEW_CURSOR_MAX_WM,
 	.default_wm = PINEVIEW_CURSOR_DFT_WM,
 	.guard_size = PINEVIEW_CURSOR_GUARD_WM,
@@ -894,6 +898,7 @@ static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 };
 static const struct intel_watermark_params g4x_wm_info = {
 	.fifo_size = G4X_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = G4X_MAX_WM,
 	.default_wm = G4X_MAX_WM,
 	.guard_size = 2,
@@ -901,6 +906,7 @@ static const struct intel_watermark_params g4x_wm_info = {
 };
 static const struct intel_watermark_params g4x_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -908,6 +914,7 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
 };
 static const struct intel_watermark_params valleyview_wm_info = {
 	.fifo_size = VALLEYVIEW_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_MAX_WM,
 	.default_wm = VALLEYVIEW_MAX_WM,
 	.guard_size = 2,
@@ -915,6 +922,7 @@ static const struct intel_watermark_params valleyview_wm_info = {
 };
 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -922,6 +930,7 @@ static const struct intel_watermark_params valleyview_cursor_wm_info = {
 };
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	.fifo_size = I965_CURSOR_FIFO,
+	.min_wm = 0,
 	.max_wm = I965_CURSOR_MAX_WM,
 	.default_wm = I965_CURSOR_DFT_WM,
 	.guard_size = 2,
@@ -929,6 +938,7 @@ static const struct intel_watermark_params i965_cursor_wm_info = {
 };
 static const struct intel_watermark_params i945_wm_info = {
 	.fifo_size = I945_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -936,6 +946,7 @@ static const struct intel_watermark_params i945_wm_info = {
 };
 static const struct intel_watermark_params i915_wm_info = {
 	.fifo_size = I915_FIFO_SIZE,
+	.min_wm = 0,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -943,6 +954,7 @@ static const struct intel_watermark_params i915_wm_info = {
 };
 static const struct intel_watermark_params i830_wm_info = {
 	.fifo_size = I855GM_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -950,6 +962,7 @@ static const struct intel_watermark_params i830_wm_info = {
 };
 static const struct intel_watermark_params i845_wm_info = {
 	.fifo_size = I830_FIFO_SIZE,
+	.min_wm = I830_MIN_WM,
 	.max_wm = I915_MAX_WM,
 	.default_wm = 1,
 	.guard_size = 2,
@@ -1003,6 +1016,9 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 		wm_size = wm->max_wm;
 	if (wm_size <= 0)
 		wm_size = wm->default_wm;
+	if (wm_size < (long)wm->min_wm)
+		wm_size = wm->min_wm;
+
 	return wm_size;
 }
 
-- 
1.7.10.4


[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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  parent reply	other threads:[~2014-06-08 21:29 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-05 16:15 [PATCH 00/15] drm/i915: Fix 830M/ns2501 for real, well almost ville.syrjala
2014-06-05 16:15 ` [PATCH 01/15] drm/i915: Use named initializers for gmch wm params ville.syrjala
2014-06-05 20:43   ` Chris Wilson
2014-06-05 21:02     ` Thomas Richter
2014-06-05 21:33     ` Bug reports on 830MG patches (thanks, but more trouble) Thomas Richter
2014-06-06  8:46       ` Ville Syrjälä
2014-06-06 17:24         ` Thomas Richter
2014-06-06 20:08           ` Ville Syrjälä
2014-06-06 21:09             ` Thomas Richter
2014-06-06 21:41               ` Ville Syrjälä
2014-06-08 21:29             ` Thomas Richter [this message]
2014-06-06 16:38     ` [PATCH 01/15] drm/i915: Use named initializers for gmch wm params Daniel Vetter
2014-06-05 16:15 ` [PATCH 02/15] drm/i915: Fix gen2 planes B and C max watermark value ville.syrjala
2014-06-05 16:15 ` [PATCH 03/15] drm/i915: Don't get hw state from DVO chip unless DVO is enabled ville.syrjala
2014-06-06 16:39   ` Daniel Vetter
2014-06-05 16:15 ` [PATCH 04/15] drm/i915: ns2501 is on DVOB ville.syrjala
2014-06-06 16:57   ` Daniel Vetter
2014-06-06 21:46     ` Ville Syrjälä
2014-06-05 16:15 ` [PATCH 05/15] drm/i915: Enable DVO between mode_set and dpms hooks ville.syrjala
2014-06-05 16:15 ` [PATCH 06/15] drm/i915: Don't call DVO mode_set hook on DPMS changes ville.syrjala
2014-06-05 16:15 ` [PATCH 07/15] drm/i915: Kill useless ns2501_dump_regs ville.syrjala
2014-06-05 16:15 ` [PATCH 08/15] drm/i915: Rewrite ns2501 driver a bit ville.syrjala
2014-06-05 16:15 ` [PATCH 09/15] drm/i915: Ignore VBT int_crt_support on 830M ville.syrjala
2014-06-06 17:00   ` Daniel Vetter
2014-06-06 19:44     ` [PATCH v2 " ville.syrjala
2014-06-06 20:13       ` Daniel Vetter
2014-06-07 20:37         ` [Patch] Add minimum watermark level for I830 Thomas Richter
2014-06-06 21:15       ` [PATCH v2 09/15] drm/i915: Ignore VBT int_crt_support on 830M Bob Paauwe
2014-06-06 22:23         ` Daniel Vetter
2014-06-06 22:51           ` Jesse Barnes
     [not found]         ` <2094_1402093395_53923F53_2094_10301_1_CAKMK7uGAnNP4VR9+zXd0KD5v0Vo=XuDS=NhRNFRqHKcae7T4XQ@mail.gmail.com>
2014-06-07 17:32           ` Thomas Richter
2014-10-24 13:23       ` Jani Nikula
2014-10-24 14:11         ` Ville Syrjälä
2014-06-05 16:15 ` [PATCH 10/15] drm/i915: Fix DVO 2x clock enable " ville.syrjala
2014-06-05 16:16 ` [PATCH 11/15] Revert "drm/i915: Nuke pipe A quirk on i830M" ville.syrjala
2014-06-05 16:16 ` [PATCH 12/15] drm/i915: Add pipe B force quirk for 830M ville.syrjala
2014-06-05 16:16 ` [PATCH 13/15] drm/i915: Eliminate rmw from .update_primary_plane() ville.syrjala
2014-06-06  0:02   ` Matt Roper
2014-06-06 19:45   ` [PATCH v2 " ville.syrjala
2014-06-05 16:16 ` [PATCH 14/15] drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane() ville.syrjala
2014-06-06  0:02   ` Matt Roper
2014-06-06  8:40     ` Ville Syrjälä
2014-06-06 19:46     ` [PATCH v2 " ville.syrjala
2014-06-05 16:16 ` [PATCH 15/15] drm/i915: Check pixel clock in ns2501 mode_valid hook ville.syrjala
2014-06-06 19:47 ` [PATCH 16/15] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off() ville.syrjala
2014-06-06 19:47   ` [PATCH 17/15] drm/i915: Disable double wide even when leaving the pipe on ville.syrjala
2014-06-06 22:09     ` [PATCH v2 " ville.syrjala
2014-06-08 23:14       ` Deadlock in intel_enable_pipe_a() Thomas Richter
2014-06-09  6:47         ` [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc() Chris Wilson
2014-06-09  8:30           ` Ville Syrjälä
2014-06-09  8:50             ` Chris Wilson
     [not found]             ` <28223_1402303866_5395757A_28223_3428_1_20140609085045.GE16767@nuc-i3427.alporthouse.com>
2014-06-09 10:57               ` Partial success - Fixing resume from s2ram on S6010 Thomas Richter
2014-06-09 11:08                 ` Ville Syrjälä
     [not found]                 ` <28223_1402312148_539595D3_28223_4884_1_20140609110857.GM27580@intel.com>
2014-06-09 11:19                   ` Thomas Richter
2014-06-09 11:31                     ` Ville Syrjälä
     [not found]                     ` <2086_1402313568_53959B5F_2086_895_1_20140609113155.GN27580@intel.com>
2014-06-09 12:33                       ` Thomas Richter
2014-06-09 12:57                       ` Thomas Richter
2014-06-09 18:41                       ` Thomas Richter
2014-06-09 19:46                         ` [PATCH] drm/i915: Init important ns2501 registers ville.syrjala
     [not found]                         ` <28223_1402343538_53961072_28223_7661_1_1402343204-28608-1-git-send-email-ville.syrjala@linux.intel.com>
2014-06-09 20:58                           ` Thomas Richter
2014-06-09 22:29                           ` Thomas Richter
2014-06-10 14:04                             ` Ville Syrjälä
     [not found]                             ` <29040_1402409145_539710B9_29040_2220_1_20140610140430.GD27580@intel.com>
2014-06-10 16:38                               ` Thomas Richter
2014-06-18 16:03                       ` i830GM on IBM R31 works with alm_fixes5 repository Thomas Richter
2014-06-10  7:02             ` [PATCH] drm/i915: Avoid double mutex lock applying pipe A quirk during sanitize_crtc() Daniel Vetter
2014-06-10  8:53               ` Ville Syrjälä
2014-06-10  9:22                 ` Daniel Vetter
2014-06-10  6:59           ` Daniel Vetter
2014-06-10  7:13             ` Chris Wilson
2014-06-06 19:47   ` [PATCH 18/15] drm/i915: Preserve VGACNTR bits from the BIOS ville.syrjala

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