Re: [PATCH] drm/i915: Init important ns2501 registers

[Thomas Richter <thor@math.tu-berlin.de>]

Hi Ville,

> Either pipe can drive DVO just fine. Looks like it's using pipe A in
> your register dump, and all the registers look fine to me. Well, DPLL B
> VCO enable is off since we don't currently have a mechanism to kick pipe
> B into action during resume/load. In theory that would need to be enabled
> as well.
>
> Can you see if a simple 'intel_reg_write 0x6018 0xc08b0000' fixes the
> problem?

Nope. I created a little script that wrote the previous data back into 
the chipset, but that did not cure the problem. The only register I 
could not write to was CACHEMODE (IIRC, this was the name intel_reg_dump 
gave). The plane pointers and cursor pointers were different, too, but 
that should not be critical.

> And if not, I'd like to see a diff of register dumps between working and
> non working setups.

I afraid the S6010 is out of reach for the next three weeks, but I 
should have a complete register dump attached to my previous mail from 
yesterday night (or this morning, to be precise).

I can now try on the R31, but I don't remember having seen anything like 
it there. It does *not* look like the flickering of the misaligned 
watermark registers - on the console it really looks like bad HSYNC on a 
TV (tearing across horizontal lines, and massive misalignments of the 
very first lines of the screen). Within X, it causes the screen to jump 
to the right by about 64(?)128(?) pixels. The problem does not disappear 
by using a different resolution or restarting X. It remains permanent 
until the next boot.

Greetings,
	Thomas