From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak S Subject: Re: [PATCH 01/40] drm/i915: Try to populate mem_freq for chv Date: Sat, 12 Jul 2014 18:57:54 +0530 Message-ID: <53C137DA.2060609@linux.intel.com> References: <1403910271-24984-1-git-send-email-ville.syrjala@linux.intel.com> <1403910271-24984-2-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2031360438==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A8786E25C for ; Fri, 11 Jul 2014 06:32:50 -0700 (PDT) In-Reply-To: <1403910271-24984-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============2031360438== Content-Type: multipart/alternative; boundary="------------070101020203080801040308" This is a multi-part message in MIME format. --------------070101020203080801040308 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > mem_freq is needed to decode the GPU freq opcodes. > > FIXME: Punit reg seems to contain garbage so this isn't right > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > index 07c040c..ef00756 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct = drm_device *dev) > static void cherryview_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > + u32 val; > + > + mutex_lock(&dev_priv->rps.hw_lock); > + val =3D vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > + mutex_unlock(&dev_priv->rps.hw_lock); > + switch ((val >> 6) & 3) { > + case 0: > + case 1: > + dev_priv->mem_freq =3D 800; > + break; > + case 2: > + dev_priv->mem_freq =3D 1066; > + break; > + case 3: > + dev_priv->mem_freq =3D 1333; > + break; > + } > + DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); > =20 > I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > =20 Added the right way of getting the mem_freq for CHV *http://lists.freedesktop.org/archives/intel-gfx/2014-July/048897.html* --------------070101020203080801040308 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

mem_freq is needed to decode the GPU freq opcodes.

FIXME: Punit reg seems to contain garbage so this isn't right

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel=
_pm.c
index 07c040c..ef00756 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct dr=
m_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv =3D dev->dev_private;
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val =3D vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq =3D 800;
+		break;
+	case 2:
+		dev_priv->mem_freq =3D 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq =3D 1333;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
=20
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
=20

Added the right way of getting the mem_freq for CHV
http://lists.freedes=
ktop.org/archives/intel-gfx/2014-July/048897.html
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