From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kumar, Shobhit" Subject: Re: [PATCH 1/3] drm/i915: Add get_config implementation for DSI encoder Date: Mon, 14 Jul 2014 20:06:31 +0530 Message-ID: <53C3EAEF.7090805@intel.com> References: <1405165643-13189-1-git-send-email-shobhit.kumar@intel.com> <1405165643-13189-2-git-send-email-shobhit.kumar@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E1FE6E2F1 for ; Mon, 14 Jul 2014 07:36:35 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: Jani Nikula , Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org On 7/12/2014 5:28 PM, Daniel Vetter wrote: > On Sat, Jul 12, 2014 at 1:47 PM, Shobhit Kumar wrote: >> Call to vlv_crtc_clock_get is not needed for DSI and was causing dpio >> read WARN dumps as well. Absence of ->get_config was casuing othet WARN >> dumps as well. With this the last of the known WARN dumps for DSI should >> be fixed. >> >> Signed-off-by: Shobhit Kumar >> --- >> drivers/gpu/drm/i915/intel_display.c | 7 +++--- >> drivers/gpu/drm/i915/intel_dsi.c | 45 ++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_dsi.h | 3 +++ >> drivers/gpu/drm/i915/intel_dsi_pll.c | 4 +++- >> 4 files changed, 55 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index fe6f1db..3d0ea7c 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -6309,9 +6309,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, >> >> if (IS_CHERRYVIEW(dev)) >> chv_crtc_clock_get(crtc, pipe_config); >> - else if (IS_VALLEYVIEW(dev)) >> - vlv_crtc_clock_get(crtc, pipe_config); >> - else >> + else if (IS_VALLEYVIEW(dev)) { >> + if (!intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) >> + vlv_crtc_clock_get(crtc, pipe_config); > > If I understand the logic correctly we don't even enable the DPLL for > dsi, i.e. bit31 is clear. So instead of this sw-side check (which is > fragile since it depends upon corrected encoder->pipe links in our > data structures) we should instead check bit 31 in vlv_crtc_clock_get > and just bail out without reading out hw settings. Yeah, sounds better will do this. > > The goal of the hw state cross-check is to check the hw state, so > wherever possible we should rely 100% on available information in the > hw and not on software tracking. Got it. > >> + } else >> i9xx_crtc_clock_get(crtc, pipe_config); >> >> return true; >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c >> index bfcefbf..61da0e5 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi.c >> +++ b/drivers/gpu/drm/i915/intel_dsi.c >> @@ -351,9 +351,54 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, >> static void intel_dsi_get_config(struct intel_encoder *encoder, >> struct intel_crtc_config *pipe_config) >> { >> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; >> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> + u32 dsi_clock, pclk; >> + u32 pll_ctl, pll_div; >> + u32 m = 0, p = 0; >> + int refclk = 25000; >> + int i; >> + >> DRM_DEBUG_KMS("\n"); >> >> /* XXX: read flags, set to adjusted_mode */ >> + pipe_config->quirks = 1; > > Nack. First you need to use one of the symbolic quirk definitions > (there's a bunch of them). Second this needs a comment why exactly we > need the quirk (which really only should be used if there's no way to > read a given piece of state back from the hw). Okay, in MIPI we have sync events going as short packets. In that case I think it should be okay to use PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS ? > >> + >> + memset(&pipe_config->dpll_hw_state, 0, >> + sizeof(pipe_config->dpll_hw_state)); >> + >> + mutex_lock(&dev_priv->dpio_lock); >> + pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); >> + pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); >> + mutex_unlock(&dev_priv->dpio_lock); >> + >> + pll_ctl &= ~(DSI_PLL_CLK_GATE_DSI0_DSIPLL | DSI_PLL_VCO_EN); >> + pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); >> + >> + while (pll_ctl) { >> + pll_ctl = pll_ctl >> 1; >> + p++; >> + } >> + p--; >> + >> + for (i = 0; i < num_lfsr_converts; i++) { >> + if (lfsr_converts[i] == pll_div) >> + break; >> + } >> + >> + if (i == num_lfsr_converts) { >> + DRM_ERROR("wrong m_seed programmed\n"); >> + return; >> + } >> + >> + m = i + 62; >> + >> + dsi_clock = (m * refclk) / p; >> + pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, >> + pipe_config->pipe_bpp); >> + >> + pipe_config->adjusted_mode.crtc_clock = pclk; >> + pipe_config->port_clock = pclk; >> } >> >> static enum drm_mode_status >> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h >> index 31db33d..e0c16b0 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi.h >> +++ b/drivers/gpu/drm/i915/intel_dsi.h >> @@ -130,6 +130,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) >> return container_of(encoder, struct intel_dsi, base.base); >> } >> >> +extern const u32 lfsr_converts[]; >> +extern const int num_lfsr_converts; >> + >> extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); >> extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c >> index ba79ec1..78449ea 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c >> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c >> @@ -43,13 +43,15 @@ struct dsi_mnp { >> u32 dsi_pll_div; >> }; >> >> -static const u32 lfsr_converts[] = { >> +const u32 lfsr_converts[] = { >> 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ >> 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ >> 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ >> 71, 35 /* 91 - 92 */ >> }; > > Optional bikeshed: I'd extract the dsi pll read-out code into a helper > function so that all the pll code is in this file and we don't need to > export internal details. The get_hw_state function in intel_dsi.c > would then use that to compute pclk and just store that at the right > places in the pipe config. Yeah will correct this as well. Regards Shobhit