From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jindal, Sonika" Subject: Re: [PATCH 0/7] Future preparation patches Date: Fri, 18 Jul 2014 16:53:34 +0530 Message-ID: <53C903B6.3060608@intel.com> References: <1405661650-5771-1-git-send-email-sonika.jindal@intel.com> <20140718105616.GB31263@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 11D886E2E4 for ; Fri, 18 Jul 2014 04:23:37 -0700 (PDT) In-Reply-To: <20140718105616.GB31263@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 7/18/2014 4:26 PM, Damien Lespiau wrote: > On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote: >> From: Sonika Jindal >> >> This series prepares future platform enabling by changing HAS_PCH_SPLIT to more >> appropriate check since the code accessed may not have anything to do with >> having PCH or not. > > Hi Sonika, > > HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the > Ibex Peak PCH. > > In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5 > then. > I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to (gen > 5 && !(IS_VALLEYVIEW) ) So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW)) -Sonika