[PATCH 0/7] Future preparation patches

[PATCH 0/7] Future preparation patches

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
appropriate check since the code accessed may not have anything to do with
having PCH or not.

Sonika Jindal (7):
  drm/i915: Allowing changing of wm latencies for other valid platforms
  drm/i915: Returning the right VGA control reg for other platforms
  drm/i915: Setting legacy palette correctly for different platforms
  drm/i915: Returning from increase/decrease of pllclock when invalid
  drm/i915: Writing proper check for reading of pipe status reg
  drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms
    in
  drm/i915: Avoid incorrect returning for some platforms

 drivers/gpu/drm/i915/i915_debugfs.c  |    6 +++---
 drivers/gpu/drm/i915/i915_drv.h      |    6 +++---
 drivers/gpu/drm/i915/intel_display.c |    8 ++++----
 drivers/gpu/drm/i915/intel_hdmi.c    |    4 ++--
 4 files changed, 12 insertions(+), 12 deletions(-)

-- 
1.7.10.4

[PATCH 1/7] drm/i915: Allowing changing of wm latencies for valid platforms

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fc39610..ffb83e0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3267,7 +3267,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
 {
 	struct drm_device *dev = inode->i_private;
 
-	if (!HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen <= 5 || IS_VALLEYVIEW(dev))
 		return -ENODEV;
 
 	return single_open(file, pri_wm_latency_show, dev);
@@ -3277,7 +3277,7 @@ static int spr_wm_latency_open(struct inode *inode, struct file *file)
 {
 	struct drm_device *dev = inode->i_private;
 
-	if (!HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen <= 5 || IS_VALLEYVIEW(dev))
 		return -ENODEV;
 
 	return single_open(file, spr_wm_latency_show, dev);
@@ -3287,7 +3287,7 @@ static int cur_wm_latency_open(struct inode *inode, struct file *file)
 {
 	struct drm_device *dev = inode->i_private;
 
-	if (!HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen <= 5 || IS_VALLEYVIEW(dev))
 		return -ENODEV;
 
 	return single_open(file, cur_wm_latency_show, dev);
-- 
1.7.10.4

[PATCH 2/7] drm/i915: Returning the right VGA control reg for platforms

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 991b663..90a682c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2800,10 +2800,10 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
 {
-	if (HAS_PCH_SPLIT(dev))
-		return CPU_VGACNTRL;
-	else if (IS_VALLEYVIEW(dev))
+	if (IS_VALLEYVIEW(dev))
 		return VLV_VGACNTRL;
+	else if (INTEL_INFO(dev)->gen >= 5)
+		return CPU_VGACNTRL;
 	else
 		return VGACNTRL;
 }
-- 
1.7.10.4

[PATCH 3/7] drm/i915: Setting legacy palette correctly for different platforms

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c89b4ac..d1c7105 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3847,7 +3847,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
 	}
 
 	/* use legacy palette for Ironlake */
-	if (HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen > 5 && !IS_VALLEYVIEW(dev))
 		palreg = LGC_PALETTE(pipe);
 
 	/* Workaround : Do not read or write the pipe palette/gamma data while
-- 
1.7.10.4

[PATCH 4/7] drm/i915: Returning from increase/decrease of pllclock when invalid

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d1c7105..e259c41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8783,7 +8783,7 @@ static void intel_increase_pllclock(struct drm_device *dev,
 	int dpll_reg = DPLL(pipe);
 	int dpll;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen > 5 && !IS_VALLEYVIEW(dev))
 		return;
 
 	if (!dev_priv->lvds_downclock_avail)
@@ -8811,7 +8811,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-	if (HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen > 5 && !IS_VALLEYVIEW(dev))
 		return;
 
 	if (!dev_priv->lvds_downclock_avail)
-- 
1.7.10.4

[PATCH 5/7] drm/i915: Writing proper check for reading of pipe status reg

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e259c41..3f7089c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13244,7 +13244,7 @@ intel_display_capture_error_state(struct drm_device *dev)
 
 		error->pipe[i].source = I915_READ(PIPESRC(i));
 
-		if (!HAS_PCH_SPLIT(dev))
+		if (INTEL_INFO(dev)->gen <= 5 || IS_VALLEYVIEW(dev))
 			error->pipe[i].stat = I915_READ(PIPESTAT(i));
 	}
 
-- 
1.7.10.4

[PATCH 6/7] drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f8f4ca..2e70132 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1562,7 +1562,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 	if (IS_VALLEYVIEW(dev)) {
 		intel_hdmi->write_infoframe = vlv_write_infoframe;
 		intel_hdmi->set_infoframes = vlv_set_infoframes;
-	} else if (!HAS_PCH_SPLIT(dev)) {
+	} else if (INTEL_INFO(dev)->gen <= 5) {
 		intel_hdmi->write_infoframe = g4x_write_infoframe;
 		intel_hdmi->set_infoframes = g4x_set_infoframes;
 	} else if (HAS_DDI(dev)) {
-- 
1.7.10.4

[PATCH 7/7] drm/i915: Avoid incorrect returning for some platforms

[sonika.jindal]

From: Sonika Jindal <sonika.jindal@intel.com>

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2e70132..a15fc47 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -882,7 +882,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 	struct intel_encoder *encoder;
 	int count = 0, count_hdmi = 0;
 
-	if (!HAS_PCH_SPLIT(dev))
+	if (INTEL_INFO(dev)->gen <= 5 || IS_VALLEYVIEW(dev))
 		return false;
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
-- 
1.7.10.4

Re: [PATCH 0/7] Future preparation patches

[Damien Lespiau]

On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
> 
> This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
> appropriate check since the code accessed may not have anything to do with
> having PCH or not.

Hi Sonika,

HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the
Ibex Peak PCH.

In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5
then.

-- 
Damien

> Sonika Jindal (7):
>   drm/i915: Allowing changing of wm latencies for other valid platforms
>   drm/i915: Returning the right VGA control reg for other platforms
>   drm/i915: Setting legacy palette correctly for different platforms
>   drm/i915: Returning from increase/decrease of pllclock when invalid
>   drm/i915: Writing proper check for reading of pipe status reg
>   drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms
>     in
>   drm/i915: Avoid incorrect returning for some platforms
> 
>  drivers/gpu/drm/i915/i915_debugfs.c  |    6 +++---
>  drivers/gpu/drm/i915/i915_drv.h      |    6 +++---
>  drivers/gpu/drm/i915/intel_display.c |    8 ++++----
>  drivers/gpu/drm/i915/intel_hdmi.c    |    4 ++--
>  4 files changed, 12 insertions(+), 12 deletions(-)
> 
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/7] Future preparation patches

[Jindal, Sonika]

On 7/18/2014 4:26 PM, Damien Lespiau wrote:
> On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote:
>> From: Sonika Jindal <sonika.jindal@intel.com>
>>
>> This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
>> appropriate check since the code accessed may not have anything to do with
>> having PCH or not.
>
> Hi Sonika,
>
> HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the
> Ibex Peak PCH.
>
> In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5
> then.
>
I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to 
(gen > 5 && !(IS_VALLEYVIEW) )
So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW))

-Sonika

Re: [PATCH 0/7] Future preparation patches

[Damien Lespiau]

On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote:
> 
> 
> On 7/18/2014 4:26 PM, Damien Lespiau wrote:
> >On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote:
> >>From: Sonika Jindal <sonika.jindal@intel.com>
> >>
> >>This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
> >>appropriate check since the code accessed may not have anything to do with
> >>having PCH or not.
> >
> >Hi Sonika,
> >
> >HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the
> >Ibex Peak PCH.
> >
> >In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5
> >then.
> >
> I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to
> (gen > 5 && !(IS_VALLEYVIEW) )
> So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW))

Yes, indeed!

-- 
Damien

Re: [PATCH 0/7] Future preparation patches

[Daniel Vetter]

On Fri, Jul 18, 2014 at 02:04:56PM +0100, Damien Lespiau wrote:
> On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote:
> > 
> > 
> > On 7/18/2014 4:26 PM, Damien Lespiau wrote:
> > >On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote:
> > >>From: Sonika Jindal <sonika.jindal@intel.com>
> > >>
> > >>This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
> > >>appropriate check since the code accessed may not have anything to do with
> > >>having PCH or not.
> > >
> > >Hi Sonika,
> > >
> > >HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the
> > >Ibex Peak PCH.
> > >
> > >In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5
> > >then.
> > >
> > I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to
> > (gen > 5 && !(IS_VALLEYVIEW) )
> > So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW))
> 
> Yes, indeed!

Since the patches need to be respun anyway, I vote for the introduction of
HAS_GMCH_DISPLAY for the gen < 5 || IS_VLV condition. Since vlv (i.e. byt
+ chv) have essentially inherited the gmch display block from gen3/4. I
think that would help the readability of the code quite a bit.

Comments?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/7] Future preparation patches

[Jindal, Sonika]

On 7/18/2014 7:00 PM, Daniel Vetter wrote:
> On Fri, Jul 18, 2014 at 02:04:56PM +0100, Damien Lespiau wrote:
>> On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote:
>>>
>>>
>>> On 7/18/2014 4:26 PM, Damien Lespiau wrote:
>>>> On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@intel.com wrote:
>>>>> From: Sonika Jindal <sonika.jindal@intel.com>
>>>>>
>>>>> This series prepares future platform enabling by changing HAS_PCH_SPLIT to more
>>>>> appropriate check since the code accessed may not have anything to do with
>>>>> having PCH or not.
>>>>
>>>> Hi Sonika,
>>>>
>>>> HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the
>>>> Ibex Peak PCH.
>>>>
>>>> In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5
>>>> then.
>>>>
>>> I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to
>>> (gen > 5 && !(IS_VALLEYVIEW) )
>>> So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW))
>>
>> Yes, indeed!
>
> Since the patches need to be respun anyway, I vote for the introduction of
> HAS_GMCH_DISPLAY for the gen < 5 || IS_VLV condition. Since vlv (i.e. byt
> + chv) have essentially inherited the gmch display block from gen3/4. I
> think that would help the readability of the code quite a bit.
>
> Comments?
> -Daniel
>
Ok, I will add this and send the patches again.

-Sonika