From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Siluvery, Arun" Subject: Re: WAs in init_clock_gating? Date: Thu, 24 Jul 2014 13:41:54 +0100 Message-ID: <53D0FF12.80306@linux.intel.com> References: <92648605EABDA246B775AAB04C95A7A3137EB57C@IRSMSX103.ger.corp.intel.com> <20140707205008.GD17271@phenom.ffwll.local> <20140707141641.44e7c407@jbarnes-desktop> <53D0E33F.4090705@linux.intel.com> <20140724123319.GA4747@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id DE96A6E2CD for ; Thu, 24 Jul 2014 05:44:37 -0700 (PDT) In-Reply-To: <20140724123319.GA4747@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: "Intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On 24/07/2014 13:33, Daniel Vetter wrote: > On Thu, Jul 24, 2014 at 11:43:11AM +0100, Siluvery, Arun wrote: >> On 07/07/2014 22:24, Daniel Vetter wrote: >>> On Mon, Jul 7, 2014 at 11:16 PM, Jesse Barnes wrote: >>>> I don't think it's unreasonable to use a macro that checks a global >>>> list for whether to apply a given WA. They'll be scattered all over, >>>> but at least it'll be easy to see: >>>> 1) whether we implement a given workaround >>>> and >>>> 2) which platforms & steppings it applies to based on the table. >>> >>> Oh, I agree it's not unreasonable. But I'm kinda begging for the >>> simple solution since months (years?) and haven't gotten it, while >>> still getting a steady stream of bug reports and issues. So I've >>> readjusted my expectations ;-) >>> >>> If someone delivers the real deal I'll certainly won't reject it. >>> -Daniel >>> >> >> I am moving bdw workarounds from clock_gating fn to render ring init fn and >> testing this before and after gpu reset. > > Testing = with an igt? Because I'll ask for this ;-) Yes, triggering gpu reset with igt, at the moment the test fails because of this register. > >> One of the workaround is to disable STC optimization, reg CACHE_MODE_1 bit6 >> set to 1. I observed that some times after boot this gets reset to 0 >> (default value) even after applying workarounds; other than workarounds no >> one else seems to write to this function. >> Any ideas about this behaviour? > > gpu init tends to do this, since clock_gating is run before that. thanks, I will take a look. regards Arun > -Daniel >