Re: [PATCH v3 05/16] drm/i915: Disable double wide even when leaving the pipe on

Thomas Richter
2014-08-15T13:28:29Z

On 15.08.2014 00:21, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Disable double wide even if the pipe quirk compels us to leave the
> pipe running. Double wide has certain implications for the plane
> assignments so best keep it off.
>
> Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010
> when double wide was enabled prior to suspend.
>
> We do leave the pixel clock ticking at the original rate which would
> require double wide to be enabled. But since the planes are all disabled
> I'm hoping that the overly fast clock won't cause any problems. Seems
> to be fine so far.
>
> v2: Disable double wide also when turning the pipe off
> v3: Reorder wrt. force pipe B quirk
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>

> ---
> drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e7175ce..3eeb5ce 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2005,17 +2005,25 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
> assert_cursor_disabled(dev_priv, pipe);
> assert_sprites_disabled(dev_priv, pipe);
>
> - /* Don't disable pipe A or pipe A PLLs if needed */
> - if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
> - return;
> -
> reg = PIPECONF(cpu_transcoder);
> val = I915_READ(reg);
> if ((val & PIPECONF_ENABLE) == 0)
> return;
>
> - I915_WRITE(reg, val & ~PIPECONF_ENABLE);
> - intel_wait_for_pipe_off(crtc);
> + /*
> + * Double wide has implications for planes
> + * so best keep it disabled when not needed.
> + */
> + if (crtc->config.double_wide)
> + val &= ~PIPECONF_DOUBLE_WIDE;
> +
> + /* Don't disable pipe or pipe PLLs if needed */
> + if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE))
> + val &= ~PIPECONF_ENABLE;
> +
> + I915_WRITE(reg, val);
> + if ((val & PIPECONF_ENABLE) == 0)
> + intel_wait_for_pipe_off(crtc);
> }
>
> /*