Re: [PATCH 01/16] drm/i915: Fix gen2 planes B and C max watermark value

Thomas Richter
2014-08-15T13:25:48Z

On 15.08.2014 00:21, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The max watermark value for gen2 planes B and C is 0x1f, instead of
> the 0x3f that plane A uses.
>
> Also check against the max even if the pipe is disabled since the
> FIFO size exceeds the plane B and C max watermark value.
>

Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 12f4e14..f696b7f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -985,13 +985,20 @@ static const struct intel_watermark_params i915_wm_info = {
> .guard_size = 2,
> .cacheline_size = I915_FIFO_LINE_SIZE,
> };
> -static const struct intel_watermark_params i830_wm_info = {
> +static const struct intel_watermark_params i830_a_wm_info = {
> .fifo_size = I855GM_FIFO_SIZE,
> .max_wm = I915_MAX_WM,
> .default_wm = 1,
> .guard_size = 2,
> .cacheline_size = I830_FIFO_LINE_SIZE,
> };
> +static const struct intel_watermark_params i830_bc_wm_info = {
> + .fifo_size = I855GM_FIFO_SIZE,
> + .max_wm = I915_MAX_WM/2,
> + .default_wm = 1,
> + .guard_size = 2,
> + .cacheline_size = I830_FIFO_LINE_SIZE,
> +};
> static const struct intel_watermark_params i845_wm_info = {
> .fifo_size = I830_FIFO_SIZE,
> .max_wm = I915_MAX_WM,
> @@ -1673,7 +1680,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> else if (!IS_GEN2(dev))
> wm_info = &i915_wm_info;
> else
> - wm_info = &i830_wm_info;
> + wm_info = &i830_a_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev, 0);
> crtc = intel_get_crtc_for_plane(dev, 0);
> @@ -1688,8 +1695,14 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> wm_info, fifo_size, cpp,
> latency_ns);
> enabled = crtc;
> - } else
> + } else {
> planea_wm = fifo_size - wm_info->guard_size;
> + if (planea_wm > (long)wm_info->max_wm)
> + planea_wm = wm_info->max_wm;
> + }
> +
> + if (IS_GEN2(dev))
> + wm_info = &i830_bc_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev, 1);
> crtc = intel_get_crtc_for_plane(dev, 1);
> @@ -1707,8 +1720,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> enabled = crtc;
> else
> enabled = NULL;
> - } else
> + } else {
> planeb_wm = fifo_size - wm_info->guard_size;
> + if (planeb_wm > (long)wm_info->max_wm)
> + planeb_wm = wm_info->max_wm;
> + }
>
> DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);