From: Thomas Richter <richter@rus.uni-stuttgart.de>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org,
Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 16/16] drm/i915: Preserve VGACNTR bits from the BIOS
Date: Fri, 15 Aug 2014 15:39:16 +0200 [thread overview]
Message-ID: <53EE0D84.9010305@rus.uni-stuttgart.de> (raw)
In-Reply-To: <1408054928-24141-17-git-send-email-ville.syrjala@linux.intel.com>
On 15.08.2014 00:22, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from
> S3 unless VGACNTR has been restore to the original value. The BIOS
> value in this case was 0x0124008E. Setting the "VGA disable" bit
> doesn't interfere with the S3 resume fortunately.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Works on the S6010 as advertized, though cannot test on the R31 since it
does not resume from S3 - it does not even reach the real-mode entry
hook of the kernel.
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b1ed71e..e0f64e4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1638,6 +1638,8 @@ struct drm_i915_private {
> */
> struct workqueue_struct *dp_wq;
>
> + uint32_t bios_vgacntr;
> +
> /* Old dri1 support infrastructure, beware the dragons ya fools entering
> * here! */
> struct i915_dri1_state dri1;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 92baf6f..f154993 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12591,7 +12591,11 @@ static void i915_disable_vga(struct drm_device *dev)
> vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
> udelay(300);
>
> - I915_WRITE(vga_reg, VGA_DISP_DISABLE);
> + /*
> + * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
> + * from S3 without preserving (some of?) the other bits.
> + */
> + I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
> POSTING_READ(vga_reg);
> }
>
> @@ -12680,6 +12684,8 @@ void intel_modeset_init(struct drm_device *dev)
>
> intel_shared_dpll_init(dev);
>
> + /* save the BIOS value before clobbering it */
> + dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
> /* Just disable it once at startup */
> i915_disable_vga(dev);
> intel_setup_outputs(dev);
>
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next prev parent reply other threads:[~2014-08-15 13:39 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-14 22:21 [PATCH 00/16] drm/i915: 830M/ns201 fixes again ville.syrjala
2014-08-14 22:21 ` [PATCH 01/16] drm/i915: Fix gen2 planes B and C max watermark value ville.syrjala
2014-08-15 13:25 ` Thomas Richter
2014-08-14 22:21 ` [PATCH 02/16] drm/i915: Disable trickle feed for gen2/3 ville.syrjala
2014-08-14 22:21 ` [PATCH 03/16] drm/i915: Idle unused rings on gen2/3 during init/resume ville.syrjala
2014-08-14 22:21 ` [PATCH 04/16] drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off() ville.syrjala
2014-08-15 13:27 ` Thomas Richter
2014-08-14 22:21 ` [PATCH v3 05/16] drm/i915: Disable double wide even when leaving the pipe on ville.syrjala
2014-08-15 13:28 ` Thomas Richter
2014-08-14 22:21 ` [PATCH 06/16] drm/i915: ns2501 is on DVOB ville.syrjala
2014-08-15 13:29 ` Thomas Richter
2014-08-14 22:21 ` [PATCH 07/16] drm/i915: Enable DVO between mode_set and dpms hooks ville.syrjala
2014-08-15 13:29 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 08/16] drm/i915: Don't call DVO mode_set hook on DPMS changes ville.syrjala
2014-08-15 13:30 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 09/16] drm/i915: Kill useless ns2501_dump_regs ville.syrjala
2014-08-15 13:08 ` Thomas Richter
2014-08-15 13:31 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 10/16] drm/i915: Rewrite ns2501 driver a bit ville.syrjala
2014-08-15 13:13 ` Thomas Richter
2014-08-15 13:32 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 11/16] drm/i915: Init important ns2501 registers ville.syrjala
2014-08-15 13:18 ` Thomas Richter
2014-08-15 13:33 ` Thomas Richter
2014-09-01 8:42 ` Daniel Vetter
2014-08-14 22:22 ` [PATCH 12/16] drm/i915: Check pixel clock in ns2501 mode_valid hook ville.syrjala
2014-08-15 13:19 ` Thomas Richter
2014-08-15 13:33 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 13/16] drm/i915: Fix DVO 2x clock enable on 830M ville.syrjala
2014-08-15 13:34 ` Thomas Richter
2014-09-01 8:46 ` Daniel Vetter
2014-09-05 18:52 ` [PATCH v2 " ville.syrjala
2014-09-08 7:33 ` Daniel Vetter
2014-08-14 22:22 ` [PATCH 14/16] Revert "drm/i915: Nuke pipe A quirk on i830M" ville.syrjala
2014-08-15 13:36 ` Thomas Richter
2014-08-14 22:22 ` [PATCH v2 15/16] drm/i915: Add pipe B force quirk for 830M ville.syrjala
2014-08-15 13:37 ` Thomas Richter
2014-08-14 22:22 ` [PATCH 16/16] drm/i915: Preserve VGACNTR bits from the BIOS ville.syrjala
2014-08-15 13:39 ` Thomas Richter [this message]
2014-08-15 7:57 ` [PATCH 00/16] drm/i915: 830M/ns201 fixes again Ville Syrjälä
[not found] ` <53EE59E8.7030101@rus.uni-stuttgart.de>
[not found] ` <20140816181342.GU4193@intel.com>
2014-08-16 18:25 ` S6010 - brightness adjustment not available Thomas Richter
2014-08-16 20:34 ` Ville Syrjälä
2014-09-01 8:53 ` [PATCH 00/16] drm/i915: 830M/ns201 fixes again Daniel Vetter
2014-09-05 18:54 ` [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3 ville.syrjala
2014-09-05 19:03 ` Thomas Richter
2014-09-06 17:33 ` Ville Syrjälä
2014-09-06 17:50 ` Thomas Richter
2014-09-08 7:39 ` Daniel Vetter
2014-09-08 7:41 ` Thomas Richter
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