* [PATCH 1/4] drm/i915: Don't call gen8_fbc_sw_flush() on chv
@ 2014-09-03 11:09 ville.syrjala
2014-09-03 11:09 ` [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code ville.syrjala
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: ville.syrjala @ 2014-09-03 11:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CHV doesn't have FBC, so don't go calling gen8_fbc_sw_flush() on it.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e6cae59..83ea273 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9132,7 +9132,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_edp_psr_flush(dev, frontbuffer_bits);
- if (IS_GEN8(dev))
+ if (IS_BROADWELL(dev))
gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
}
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code
2014-09-03 11:09 [PATCH 1/4] drm/i915: Don't call gen8_fbc_sw_flush() on chv ville.syrjala
@ 2014-09-03 11:09 ` ville.syrjala
2014-09-04 11:49 ` Deepak S
2014-09-03 11:09 ` [PATCH 3/4] drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code ville.syrjala
2014-09-03 11:09 ` [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs ville.syrjala
2 siblings, 1 reply; 6+ messages in thread
From: ville.syrjala @ 2014-09-03 11:09 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
IS_GEN8() is a bad check in the forcewake code due to bdw vs. chv
differences. Use IS_BROADWELL() instead.
The only actual bug here is that we currently call
__gen7_gt_force_wake_mt_reset() on chv. On the other places we
have checked for chv before using IS_GEN8(), but change them
to use IS_BROADWELL() anyway to reduce the chance of accidents in the
future.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e81bc3b..918b761 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -101,7 +101,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
{
u32 forcewake_ack;
- if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
+ if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
forcewake_ack = FORCEWAKE_ACK_HSW;
else
forcewake_ack = FORCEWAKE_MT_ACK;
@@ -334,7 +334,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
else if (IS_GEN6(dev) || IS_GEN7(dev))
__gen6_gt_force_wake_reset(dev_priv);
- if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
__gen7_gt_force_wake_mt_reset(dev_priv);
if (restore) { /* If reset with a user forcewake, try to restore */
@@ -838,7 +838,7 @@ void intel_uncore_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev)) {
dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
- } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
+ } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
} else if (IS_IVYBRIDGE(dev)) {
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code
2014-09-03 11:09 ` [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code ville.syrjala
@ 2014-09-04 11:49 ` Deepak S
0 siblings, 0 replies; 6+ messages in thread
From: Deepak S @ 2014-09-04 11:49 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wednesday 03 September 2014 04:39 PM, ville.syrjala@linux.intel.com
wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> IS_GEN8() is a bad check in the forcewake code due to bdw vs. chv
> differences. Use IS_BROADWELL() instead.
>
> The only actual bug here is that we currently call
> __gen7_gt_force_wake_mt_reset() on chv. On the other places we
> have checked for chv before using IS_GEN8(), but change them
> to use IS_BROADWELL() anyway to reduce the chance of accidents in the
> future.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index e81bc3b..918b761 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -101,7 +101,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
> {
> u32 forcewake_ack;
>
> - if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
> + if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
> forcewake_ack = FORCEWAKE_ACK_HSW;
> else
> forcewake_ack = FORCEWAKE_MT_ACK;
> @@ -334,7 +334,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
> else if (IS_GEN6(dev) || IS_GEN7(dev))
> __gen6_gt_force_wake_reset(dev_priv);
>
> - if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
> + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
> __gen7_gt_force_wake_mt_reset(dev_priv);
>
> if (restore) { /* If reset with a user forcewake, try to restore */
> @@ -838,7 +838,7 @@ void intel_uncore_init(struct drm_device *dev)
> if (IS_VALLEYVIEW(dev)) {
> dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
> dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
> - } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
> + } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
> dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
> } else if (IS_IVYBRIDGE(dev)) {
Yup I Agree :)
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code
2014-09-03 11:09 [PATCH 1/4] drm/i915: Don't call gen8_fbc_sw_flush() on chv ville.syrjala
2014-09-03 11:09 ` [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code ville.syrjala
@ 2014-09-03 11:09 ` ville.syrjala
2014-09-03 11:09 ` [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs ville.syrjala
2 siblings, 0 replies; 6+ messages in thread
From: ville.syrjala @ 2014-09-03 11:09 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A few open coded HAS_GMCH_DISPLAY() remain in the underrun reporting
code. Convert them over.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d5ae82..b964824 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -497,7 +497,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
old = !intel_crtc->cpu_fifo_underrun_disabled;
intel_crtc->cpu_fifo_underrun_disabled = !enable;
- if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
+ if (HAS_GMCH_DISPLAY(dev))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 83ea273..0b9c9e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13036,7 +13036,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
}
}
- if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
+ if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
/*
* We start out with underrun reporting disabled to avoid races.
* For correct bookkeeping mark this on active crtcs.
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs
2014-09-03 11:09 [PATCH 1/4] drm/i915: Don't call gen8_fbc_sw_flush() on chv ville.syrjala
2014-09-03 11:09 ` [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code ville.syrjala
2014-09-03 11:09 ` [PATCH 3/4] drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code ville.syrjala
@ 2014-09-03 11:09 ` ville.syrjala
2014-09-03 13:15 ` Daniel Vetter
2 siblings, 1 reply; 6+ messages in thread
From: ville.syrjala @ 2014-09-03 11:09 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Check for !HAS_PCH_SPLIT() instead of 'gen < 5' in the PCH transcoder
enable functions.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b9c9e0..a53954c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1864,7 +1864,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
uint32_t reg, val, pipeconf_val;
/* PCH only available on ILK+ */
- BUG_ON(INTEL_INFO(dev)->gen < 5);
+ BUG_ON(!HAS_PCH_SPLIT(dev));
/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv,
@@ -1917,7 +1917,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
u32 val, pipeconf_val;
/* PCH only available on ILK+ */
- BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
+ BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs
2014-09-03 11:09 ` [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs ville.syrjala
@ 2014-09-03 13:15 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2014-09-03 13:15 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Sep 03, 2014 at 02:09:53PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Check for !HAS_PCH_SPLIT() instead of 'gen < 5' in the PCH transcoder
> enable functions.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
All four patches from this series merged, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0b9c9e0..a53954c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1864,7 +1864,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> uint32_t reg, val, pipeconf_val;
>
> /* PCH only available on ILK+ */
> - BUG_ON(INTEL_INFO(dev)->gen < 5);
> + BUG_ON(!HAS_PCH_SPLIT(dev));
>
> /* Make sure PCH DPLL is enabled */
> assert_shared_dpll_enabled(dev_priv,
> @@ -1917,7 +1917,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> u32 val, pipeconf_val;
>
> /* PCH only available on ILK+ */
> - BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
> + BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-09-03 13:15 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-09-03 11:09 [PATCH 1/4] drm/i915: Don't call gen8_fbc_sw_flush() on chv ville.syrjala
2014-09-03 11:09 ` [PATCH 2/4] drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code ville.syrjala
2014-09-04 11:49 ` Deepak S
2014-09-03 11:09 ` [PATCH 3/4] drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code ville.syrjala
2014-09-03 11:09 ` [PATCH 4/4] drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs ville.syrjala
2014-09-03 13:15 ` Daniel Vetter
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox