From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacek Danecki Subject: Re: [PATH] Correct GPU timestamp read Date: Tue, 23 Sep 2014 19:12:31 +0200 Message-ID: <5421A9FF.3000909@intel.com> References: <54204CDD.9000706@intel.com> <20140923083726.GY15734@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 780EE88A28 for ; Tue, 23 Sep 2014 10:12:59 -0700 (PDT) In-Reply-To: <20140923083726.GY15734@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 09/23/14 10:37, Daniel Vetter wrote: > On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote: >> Current implementation of reading GPU timestamp is broken. >> It returns lower 32 bits shifted by 32 bits (XXXXXXXX00000000 instead of YYYYYYYYXXXXXXXX). >> Below change is adding possibility to read hi part of that register separately. >> >> Signed-off-by: Jacek Danecki jacek.danecki@intel.com > > Needs to come with corresponding userspace using this. Beignet can use this in below function. They are using only 32 bits from timestamp register, because of kernel bug. * IVB and HSW's result MUST shift in x86_64 system */ static uint64_t intel_gpgpu_read_ts_reg_gen7(drm_intel_bufmgr *bufmgr) { uint64_t result = 0; drm_intel_reg_read(bufmgr, TIMESTAMP_ADDR, &result); /* In x86_64 system, the low 32bits of timestamp count are stored in the high 32 bits of result which got from drm_intel_reg_read, and 32-35 bits are lost; but match bspec in i386 system. It seems the kernel readq bug. So shift 32 bit in x86_64, and only remain 32 bits data in i386. */ #ifdef __i386__ return result & 0x0ffffffff; #else return result >> 32; #endif /* __i386__ */ } -- jacek