Re: [PATH] Correct GPU timestamp read

[Jacek Danecki <jacek.danecki@intel.com>]

On 09/25/14 14:26, Chris Wilson wrote:
> The problem is that beignet already works around the broken hw read
> whereas mesa does not. 

There is workaround in mesa already:

static uint64_t
ilo_get_timestamp(struct pipe_screen *screen)
{
   struct ilo_screen *is = ilo_screen(screen);
   union {
      uint64_t val;
      uint32_t dw[2];
   } timestamp;

   intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, &timestamp.val);

   /*
    * From the Ivy Bridge PRM, volume 1 part 3, page 107:
    *
    *     "Note: This timestamp register reflects the value of the PCU TSC.
    *      The PCU TSC counts 10ns increments; this timestamp reflects bits
    *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
    *      hours)."
    *
    * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
    * of the timestamp.  We will have to live with a timestamp that rolls over
    * every ~343 seconds.
    *
    * See also brw_get_timestamp().
    */
   return (uint64_t) timestamp.dw[1] * 80;
}


> If we apply the fix in the kernel we break the
> one user of it in beignet but fix all the existing users of mesa.

Are you talking about fix in kernel which will provide 36 bits GPU timestamp,
or about applying patch I've proposed?
If we add new register to register_whitelist, we will probably not break anything,
but we'll allow UMD's to use whole TIMESTAMP.

-- 
jacek