From mboxrd@z Thu Jan 1 00:00:00 1970 From: Clint Taylor Subject: Re: [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes Date: Mon, 06 Oct 2014 15:01:46 -0700 Message-ID: <5433114A.1010001@intel.com> References: <1411598116-4190-1-git-send-email-clinton.a.taylor@intel.com> <1411662396-10935-1-git-send-email-clinton.a.taylor@intel.com> <20140926162853.GB32511@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; Format="flowed" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id D98AC6E1FA for ; Mon, 6 Oct 2014 15:03:38 -0700 (PDT) In-Reply-To: <20140926162853.GB32511@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?windows-1252?Q?Ville_Syrj=E4l=E4?= Cc: Intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On 09/26/2014 09:28 AM, Ville Syrj=E4l=E4 wrote: > On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.taylor@intel.com wrot= e: >> From: Clint Taylor >> >> HDMI audio clock config was incorrectly choosing the default for >> pixel doubled interlaced modes. The table was missing pixel clock >> values 13.500 (27.000) and 13.513 (27.027). Luckily the default N >> value for 25.200 is the same N value for both 27MHz pixel clocks, >> a warning message was being printed with drm.debug set. >> >> ver2: Use 13500 * 1001 / 1000 instead of 13513 constant. >> >> Cc: Jani Nikula >> >> Signed-off-by: Clint Taylor >> --- >> drivers/gpu/drm/i915/intel_display.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915= /intel_display.c >> index 858011d..e76a4106 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -7872,6 +7872,8 @@ static struct { >> { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, >> { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_1483= 52 }, >> { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, >> + { 13500, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, >> + { 13500 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, > > We have double clocked modes where the non-doubled clock is already > 27MHz so this seems like a bandaid for one particular case rather than a > full solution. > > The HDMI specification makes it clear that the N/CTS stuff depends on > the TMDS clock and not the pixel clock, but BSpec just talks about pixel > clock without further explaining any of this stuff. So should we look > at port_clock rather than the pixel clock here? No, Since we support 12bpc we still need to only worry about the pixel = clock. TMDS clock and port clock will be multiplied by 1.5 in 12bpc = mode, but the N value remains the same as the 8bpc clock. -Clint > >> }; >> >> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ >> -- >> 1.7.9.5 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >