Re: [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration

From: "Singh, Gaurav K" <gaurav.k.singh@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Subject: Re: [PATCH 3/9] drm/i915: MIPI Port Ctrl related changes for dual link configuration
Date: Tue, 21 Oct 2014 12:00:30 +0530	[thread overview]
Message-ID: <5445FD86.4060300@intel.com> (raw)
In-Reply-To: <87d2almkpz.fsf@intel.com>


On 9/24/2014 2:57 PM, Jani Nikula wrote:
> On Wed, 24 Sep 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h            |    1 +
>>   drivers/gpu/drm/i915/intel_dsi.c           |   53 ++++++++++++++++++++++------
>>   drivers/gpu/drm/i915/intel_dsi.h           |    1 +
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    1 +
>>   4 files changed, 45 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index ad8179b..922d807 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6215,6 +6215,7 @@ enum punit_power_well {
>>   #define  DPI_ENABLE					(1 << 31) /* A + B */
>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>>   #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
>> +#define  DUAL_LINK_MODE_SHIFT				26
>>   #define  DUAL_LINK_MODE_MASK				(1 << 26)
>>   #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
>>   #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index e456ca9..3b1890e 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -109,13 +109,31 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>   	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>   	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>   	enum pipe pipe = intel_crtc->pipe;
>> -	u32 temp;
>> -
>> -	/* assert ip_tg_enable signal */
>> -	temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
>> -	temp = temp | intel_dsi->port_bits;
>> -	I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
>> -	POSTING_READ(MIPI_PORT_CTRL(pipe));
>> +	u32 temp, port_control = 0;
>> +
>> +	if (intel_dsi->dual_link) {
>> +		port_control = (intel_dsi->dual_link - 1)
>> +					<< DUAL_LINK_MODE_SHIFT;
>> +		port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B :
>> +					LANE_CONFIGURATION_DUAL_LINK_A;
>> +		/*For Port A */
>> +		temp = I915_READ(MIPI_PORT_CTRL(0));
>> +		temp = temp | port_control;
>> +		I915_WRITE(MIPI_PORT_CTRL(0), temp | DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(0));
>> +
>> +		/* For Port C */
>> +		temp = I915_READ(MIPI_PORT_CTRL(1));
>> +		I915_WRITE(MIPI_PORT_CTRL(1), temp | DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(1));
> This calls for a cleanup in i915_reg.h for per port vs. per transcoder
> registers. MIPI_PORT_CTRL(1) uses _TRANSCODER macro. We also have enum
> port with PORT_C == 2. This gets confusing.

Are you suggesting to use _PORT macro instead of _TRANSCODER macro?
>
>> +	} else {
>> +		/* assert ip_tg_enable signal */
>> +		temp = I915_READ(MIPI_PORT_CTRL(pipe)) &
>> +					~LANE_CONFIGURATION_MASK;
>> +		temp = temp | intel_dsi->port_bits;
>> +		I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(pipe));
>> +	}
>>   }
>>   
>>   static void intel_dsi_port_disable(struct intel_encoder *encoder)
>> @@ -123,13 +141,26 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
>>   	struct drm_device *dev = encoder->base.dev;
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>>   	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>   	enum pipe pipe = intel_crtc->pipe;
>>   	u32 temp;
>>   
>> -	/* de-assert ip_tg_enable signal */
>> -	temp = I915_READ(MIPI_PORT_CTRL(pipe));
>> -	I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
>> -	POSTING_READ(MIPI_PORT_CTRL(pipe));
>> +	if (intel_dsi->dual_link) {
>> +		/*For Port A */
>> +		temp = I915_READ(MIPI_PORT_CTRL(0));
>> +		I915_WRITE(MIPI_PORT_CTRL(0), temp & ~DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(0));
>> +
>> +		/* For Port C */
>> +		temp = I915_READ(MIPI_PORT_CTRL(1));
>> +		I915_WRITE(MIPI_PORT_CTRL(1), temp & ~DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(1));
>> +	} else {
>> +		/* de-assert ip_tg_enable signal */
>> +		temp = I915_READ(MIPI_PORT_CTRL(pipe));
>> +		I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
>> +		POSTING_READ(MIPI_PORT_CTRL(pipe));
>> +	}
>>   }
>>   
>>   static void intel_dsi_device_ready(struct intel_encoder *encoder)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 587e71f..950ab41 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -101,6 +101,7 @@ struct intel_dsi {
>>   	u8 clock_stop;
>>   
>>   	u8 escape_clk_div;
>> +	u8 dual_link;
>>   	u32 port_bits;
>>   	u32 bw_timer;
>>   	u32 dphy_reg;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index 051bfff..d424ebc 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -283,6 +283,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
>>   	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
>>   	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
>>   	intel_dsi->port = 0;
>> +	intel_dsi->dual_link = mipi_config->dual_link;
>>   
>>   	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>>   		bits_per_pixel = 18;
>> -- 
>> 1.7.9.5
>>
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